What clock source does CPU2 select coming out of CStop on the STM32WB55 if the HSE is not enabled?

[User1655833706281357277]

I am trying to get to the lowest possible power consumption on a WB55 NUCLEO board while the BLE is advertising every three seconds and waking up on the RTC every second.  I have the NUCLEO booting up on the HSE clock, and the stm32_lpm_if.c code switches from HSE to HSI and back as it enters and exits STOP2.  Re-enabling HSE takes about 24 ms and consumes significant current, giving me an average of about 62 uA in this mode.  I’ve found that if don’t enable the HSE, but stay on the HSI the current drops to about 10.5 uA.   The BLE radio functions normally, and I can connect and disconnect and return to the 10.5 uA advertising mode.  Is CPU2 somehow choosing the LSE clock to run on when it exits STOP2 and the HSE is not available?   What is going on?  The documentation is adamant about needing 32MHz for the system clock when running the radio.

[User1655833706281357277]

More information:  After putting SYSCLK out on an MCO pin, it looks like CPU1 is running on a 32 MHz clock coming out of STOP2.   Without explicit code to enable the HSE.  So is CPU2 doing this?   Either way, the busywait the HSE enable code is doing waiting for stabilization is costing about 6x the power consumption.   Is there a document somewhere I’m missing?  What is the hardware doing?

 

[Christophe Arnal]

Hello,

CPU2 requires at least 32Mhz to be operational.

It is not possible to have radio operation without a 32Mhz clock.

Therefore, each time CPU2 exits from Stop mode, it checks if the system clock is already selected to be at least 32Mhz (i.e either HSE or PLL).

if this is not the case, that means CPU1 is in STOP mode and CPU2 will switch to HSE on its own.

 

Since CPU2 is a closed system, there is no detailed information on the algorithm used. However, AN5289 described all algorithm that shall be followed by CPU1.

 

Regards.

Regards.

[User1655833706281357277]

It would be nice if you guys opened CPU2 up a little.   There’s a pretty serious power penalty for using your example code.  Among other things.

[Christophe Arnal]

Hello,

Which the serious power penalty are you facing when using the provided example ?

All application example shall be able to reach the maximum low power efficiency ( as long as low power mode is enabled).

The concept is that the application should consider the CPU2 as a peripheral and shall not worry about CPU2 power management. 

Since there is a CPU in that peripheral, there are a couple of rules and semaphore to be used. All these mechanism are described in AN5289 and you should not need more details.

If you are facing any low power penalty, feel free to post on this forum (in another thread) as this is not expected.

Regards.

 

[User1655833706281357277]

The issue is the busywait  waiting for the HSE clock to become stable as the mcu comes out of sleep in the example code.  That wait is longish and consumes power.