Unable to set clock frequency above 32MHz

[Adomin]

Hey guys,

Im running into some issues with trying to set the clock speed of my stm32wb55 chip above 32MHz on my custom board.

Here is my baremetal startup code that works using MSI as sysclk

void __attribute__((naked)) Reset_Handler()
{
 __asm__("ldr r0, =_estack\n\t"
 "mov sp, r0");
 
 // Copy data section from flash memory to ram
 uint32_t data_section_size = _edata - _sdata;
 memcpy(_sdata, _sidata, data_section_size*4);
 
 // Zero out bss
 uint32_t bss_section_size = _ebss - _sbss;
 memset(_sbss, 0, bss_section_size*4);
 
 // Set Interrupt Vector Table Offset
 SCB->VTOR = (uint32_t)interrupt_vector_table;
 
 rcc_reset();
 RCC->CR &= ~(RCC_CR_MSIRANGE);
 // RCC_MSI_CLOCK_SPEED_32MHz = 0xa
 RCC->CR |= RCC_MSI_CLOCK_SPEED_32MHz << RCC_CR_MSIRANGE_Pos;
 main();
}

However if I change line 20 to this:

// RCC_MSI_CLOCK_SPEED_48MHz = 0xB
RCC->CR |= RCC_MSI_CLOCK_SPEED_48MHz << RCC_CR_MSIRANGE_Pos;

My program will refuse to run. Trying to step through with gdb after this line will result in a SIGTRAP.

I get the same results if I configure the PLL clock to anything greater than 32MHz and use that as my sysclk.

Any thoughts on this? Could it be an unstable power supply on my custom board?

[TDK]

Can't see what's in rcc_reset from here.

Did you follow the RM notes on increasing CPU frequency? Namely wait states.

 

Are you following the guidelines for modifying MSIRANGE? Modifying the register in a single operation rather than twice in a row is a better idea.

Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION = 0) or when MSI is

ready (MSIRDY = 1). MSIRANGE must NOT be modified when MSI is ON and NOT

ready (MSION = 1 and MSIRDY = 0).

[Adomin]

Thanks for the reply!

rcc_reset() sets all the rcc registers to their default values specified in the reference manual.

I should be following the guidelines stated there. MSI is ready at that point.

Its just strange that I can increase the clock from 4MHz on reset to anything besides values over 32MHz.

[TDK]

> I should be following the guidelines stated there.

But are you? Where do you modify wait states?

> RCC->CR &= ~(RCC_CR_MSIRANGE);

> RCC->CR |= RCC_MSI_CLOCK_SPEED_32MHz << RCC_CR_MSIRANGE_Pos;

How do you know MSI is ready between those two statements? You certainly aren't checking in the code.

[Adomin]

Fair enough.

I added in the MSI ready check and set the wait state to 2 and the firmware runs perfectly fine now

Thanks for your help!