TIM interrupt, sequencer, SPI_SCK

[ZWH.1]

Hi!

I am using P-nucleo WB55 board to develop BLE application.

1 I use TIM2 to generate a interrupt where I use SPI to read external ADC data. However, I found that the time period between SPI SCK signal and rising edge of TIM's PWM is varying. as shown in the attached figure.

Below is a part of the code in TIM interrupt function:

// HAL_TIM_IRQHandler(&htim2);
 
 /* USER CODE BEGIN TIM2_IRQn 1 */
 
	SPI1->CR1 |= SPI_CR1_SPE;
 
	while(!(SPI1->SR&SPI_SR_RXNE));
 
	SPI1->CR1 &=(~SPI_CR1_SPE);
 
	Dout_a[i]=SPI1->DR;
 

SPI signal is enable right after the interrupt. There is no code before enabling SPI signal. Why the time is varying?

Can a task in sequencer be interrupted, when it is running?

Sequencer tasks are running in parallel with the interrupt or in series with the interrupt?

[TDK]

The Cortex-M4 has a relatively small and consistent ISR delay. There are some things that can affect this such as wait states, but the effect is minimal.

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/beginner-guide-on-interrupt-latency-and-interrupt-latency-of-the-arm-cortex-m-processors

I would assume the RTOS is causing the delay. If the ISR priority is max and there is still significant jitter, the OS might be briefly halting interrupts during a critical section.

> Sequencer tasks are running in parallel with the interrupt or in series with the interrupt?

Only one thing can run at a time. When the ISR is running, everything else is on hold.

[ZWH.1]

Hi!

Thank you for the reply�?

​

​How long is the max delay caused by RTOS? Can it be up to 500 to 700 ns? When the M4 core is running on 64 MHz, 500 ns can accommodate approximate 300 machine clocks.

[TDK]

I'm not an RTOS expert and have very little interest in them. I imagine the answer to this would very much be application and implementation dependent.

[Christophe Arnal]

Hello,

The Sequencer is a packaging of a simple standard while(1) loop. The behavior is similar to :

while(1)
{
task1();
task2();
task3();
}

So, any interrupt handler can interrupt a running task in the background. The other way around is not possible. A running interrupt handler cannot be interrupted by a background task.

Regards.

[ZWH.1]

HI!

Thank you for the reply!

So, does it mean that the BLE transmission task can be interrupted at any time? Even the BLE transmission is running in M0 core.

I collect data in the interrupt, and use BLE to send it out.

[Christophe Arnal]

Hello,

Each CPU has its own interrupt vector table and background scheduling. An interrupt on one core cannot delay code execution on the second core.

Both CPUs are running in parallel.

So, whatever you do on CM4 will not interrupt code execution on CM0+.

Any background task can be interrupted by an interrupt (except if running in critical section)

Regards.