STM32WLE RAM Retention Only Functional in Debug Mode

[RLind.3]

Hi there,

I am using an STM32WLE and putting it into Standby mode for extended periods of time. I am trying to retain SRAM2 while in Standby mode, and it is working while the DBGMCU_CR_DBG_STANDBY bit is set. However, when I clear the bit SRAM2 is no longer retained.

I have set the PWR_CR3_RRS bit, the option byte SRAM_RST is set by default, and I have set my linker to not initialise the portion of SRAM2 that I wish to retain.

Does anyone have any ideas as to why debug mode could have such an impact on RAM retention?

Thanks,

Rebecca

[Danish1]

How strongly do you know you are putting the stm32 into Standby-with-SRAM2 rather than shutdown?

(Table 36 of Reference Manual section 5.4 "Low Power Modes").

I guess DBGMCU_CR_DBG_STANDBY is forcing the LPR voltage-regulator to stay on.

Do you write directly to the peripherals e.g. PWR->CR3 or do you use e.g. ST's HAL libraries for that. The reason I ask is that I can't find enough about the HAL libraries for how to use them the way I want (rather than just copying examples) so I often refer to the Reference Manual and either write the registers directly or reverse-engineer HAL to see what precisely I need to do to get the register values I want.

Hope this helps,

Danish

[RLind.3]

Hi Danish,

When the MCU wakes, the PWR_EXTSCR_C1SBF is set, so I believe it is in Standby rather than Shutdown.

Setting DBGMCU_CR_DBG_STANDBY maintains power to the core and keeps the processor clocks active. From the reference manual, "The STM32WLEx devices include power saving features that allow the core power domain to be switched off or stopped when not required. If the power is switched off, or the core is not clocked, all debug components are inaccessible to the debugger. To avoid this, power saving mode emulation has been implemented. If emulation is enabled for a domain, the domain still enters power saving mode, but its clock and power are maintained. In other words, the domain behaves as if it is in power saving mode, but the debugger does not lose the connection." In theory, the PWR_CR3_RRS bit should keep the LP regulator running for the SRAM regardless of whether the DBGMCU_CR_DBG_STANDBY bit is set.

I write directly to the peripherals and registers as I have had similar issues with using the HAL.

Thanks,

Rebecca

[RLind.3]

The problem has been resolved. It was an error in my linker, the address I had for SRAM2 was wrong. Fixing the address fixed the problem and my SRAM2 is now retained regardless of DBGMCU_CR_DBG_STANDBY.