STM32WB55 Random Core2 Hard Faults

[Aku]

Hi,

we've been testing STOP2 modes and faced random core2 crashes.

We use radio stack 1.15.0 Light

Crash data at 0x20030000: 0x1170fd0f   0x00000000   0x00000939   0x2003fa20

Any ideas?

[Remy ISSALYS]

Hello,

When the hardfault occurs, can you check the value of FLASH_SR registrer?

Best Regards

[Aku]

Hi Remi,

FLASH_SR were containing 0x0

We are using keystore in RAM, so core2 shouldn't write anything to flash.

Also no HSEMs were locked by core2

[Remy ISSALYS]

Hello,

How did you enter in stop2 low power mode? Are you using the low power manager used in STM32CubeWB package example? You can look BLE_HeartRate example that allow to reach stop2 low power mode.

Best Regards

[Aku]

Yes, we do enter STOP2 low power mode (deep sleep).

No, we don't use LPM from cube.

Our code is kinda based on BLE HeartRate, but whole system is much more sophisticated.

Here is how we do transition to deep sleep STOP2:

• os hook: https://github.com/flipperdevices/flipperzero-firmware/blob/0.82.2-rc/firmware/targets/f7/furi_hal/furi_hal_os.c#L132
• clock: https://github.com/flipperdevices/flipperzero-firmware/blob/0.82.2-rc/firmware/targets/f7/furi_hal/furi_hal_clock.c#L204
• https://github.com/flipperdevices/flipperzero-firmware/blob/0.82.2-rc/firmware/targets/f7/furi_hal/furi_hal_power.c#L174

[Remy ISSALYS]

Hello,

After how long does the hard fault appear? Do you have a precise scenario that generate the hard fault?

Best Regards

[Aku]

Some device crashes every couple hours, other can work days. We don't have exact way to reproduce it.

[Remy ISSALYS]

Hello,

Using your code to enter/exit in stop2 low power mode, I reproduce the hard fault on nucleo-wb55, issue is under investigation. I keep you inform as soon as possible.

Best Regards

[Aku]

Awesome, waiting for results. Also can you link this to case 00178410 ?

[Remy ISSALYS]

Hello,

Issue is still under investigation to find the root causes.

Best Regards

[Aku]

Any updates? This issues is severely affects our customers and we literally tried everything on our side. Most infuriating is that we can not restart core2 without restarting whole MCU.

[Aku]

Issue was caused by incorrect clocking scheme caused by clock configuration condition race on deep sleep enter/exit. Happens only if 64 MHz PLL used for system clock.

Solution is kinda tricky: core1 is not allowed to perform switch to PLL, instead it must use SHCI_C2_SetSystemClock(available in radio stack 1.17.3 or later) to perform transition. Also if FreeRTOS used then IPCC SYS must be used in blocking mode since interrupts are not available at the moment of transition to stop mode.