STM32WB55 IPCC Shared Memory

[DS.4]

Is there a document describing all the shared memory between CPU1 and CPU2?

Looked at AN5289 , but did not find any memory table map.

How does CPU2 know where to put the answers for IPCC CPU1 requests?

I see a lot of "PLACE_IN_SECTION" in the code not knowing is it shared or not.

[Remi QUINTIN]

You may have a look at AN5185 “How to flash a WB device�? where the structure of the shared SRAM2 memory is described or at least the shared table for inter-processor communication .listing all communication data buffers.

Communication data buffers are pointed to by a lookup table for which the address is determined by an offset from the start of the SRAM2 memory. This offset is set in the option byte: IPCCDBA (IPCC mailbox data buffer base address).

This shared table is set up by the application (on M4 core)and then read by the RF stack (M0+ core) for further communication.

PLACE_IN SECTION pragma are not shared but it is possible the same section is also identify /assigned in a specific area in the other core.

But this is less flexible than the use of the shared table to exchange all information related to shared data buffers.