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JR2963
Senior II
May 30, 2024
Solved

STM32WB BLE - HardFault

Hi,

I am working on BLE with STM32W55RGV. I have loaded FUS+Full_BLE_stack into the M0+ core. In the M4 core, I have my own application, but I always get a HardFault when I call this function, as shown in the picture (SendCmd(uint16_t opcode, uint8_t plen, void *param)). It is basically first entry function to try to do anything with BLE. At that moment, opcode = 64535 and plen = 0. Could this be related to IPCC? I have enabled interrupts for both RX and TX, and I have also increased the BLE FreeRTOS stack to 1024.

Alos I added breakpoint to APPE_SysUserEvtRx - to see if CPU2 is ready (was mentioned in  STM video tutorial for HeartRate monitor), but the function is not called..hf2.png

I have no idea how to move forward.

Thanks!

HF.png

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JR2963
JR2963Best answer
Senior II
May 30, 2024

Do not how is it related to it, but this is solution:

 

 

void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
#if 0 
 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
 HAL_TIM_IRQHandler(&htim1);
 HAL_TIM_IRQHandler(&htim17);
 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
#endif // Endof comment out

 if(htim1.Instance != NULL)
 {
 HAL_TIM_IRQHandler(&htim1);
 }

 if(htim17.Instance != NULL)
 {
 HAL_TIM_IRQHandler(&htim17);
 }
 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}

 

 

 

1 reply

JR2963
JR2963AuthorBest answer
Senior II
May 30, 2024

Do not how is it related to it, but this is solution:

 

 

void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
#if 0 
 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
 HAL_TIM_IRQHandler(&htim1);
 HAL_TIM_IRQHandler(&htim17);
 /* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
#endif // Endof comment out

 if(htim1.Instance != NULL)
 {
 HAL_TIM_IRQHandler(&htim1);
 }

 if(htim17.Instance != NULL)
 {
 HAL_TIM_IRQHandler(&htim17);
 }
 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
 /* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}