SPI2 working issues with STM32WB55RG

[SS_135]

Hi Team,

By using STM32WB55RG , SPI1 is connected to LCD and is working fine and SPI2 is connected to external flash memory, It is not working.

Note- Same flash memory is working on SPI1.

Kindly let us know any configurations needed to work on SPI2 on the board.

Also attached the schematics for the MCU SPI interface for your reference .

Kindly advise to proceed further

Regards

Sudeendra S

[JPhan.1]

Hello Group,

I have the same problem when working BLE + SPI in the board stm32wb55RG.

I tried to use BLE and SPI in STM32WB55RG but it has errors after generated code.

The error is: HAL_SPI_Init(..) because it doesn't have the file stm32wbxx_hal_spi.c

When I manually copy and paste this file stm32wbxx_hal_spi.c into the project driver, then I cannot debug and my board cannot work anymore.

Any advisors?

Anybody has generated the code of BLE + SPI in this Nucleo board STM32WB55RG?

Thanks a lot for your time,

Jack

[LMart.15]

The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.3 and with IEEE 802.15.4-2011. They contain a dedicated Arm® Cortex®-M0+ for performing all the real-time low layer operation.

The devices are designed to be extremely low-power and are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm®single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.

The devices embed high-speed memories (up to 1 Mbyte of flash memory for STM32WB55xx, up to 512 Kbytes for STM32WB35xx, up to 256 Kbytes of SRAM for STM32WB55xx, 96 Kbytes for STM32WB35xx), a Quad-SPI flash memory interface (available on all packages) and an extensive range of enhanced I/Os and peripherals.

Direct data transfer between memory and peripherals and from memory to memory is supported by fourteen DMA channels with a full flexible channel mapping by the DMAMUX peripheral.

The devices feature several mechanisms for embedded flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access.

The two AES encryption engines, PKA, and RNG enable lower layer MAC and upper layer cryptography. A customer key storage feature may be used to keep the keys hidden.

The devices offer a fast 12-bit ADC and two ultra-low-power comparators associated with a high accuracy reference voltage generator.

These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers.