QuadSPI interface to Multiple PSRAM devices

[WQ_it]

Hi, we are going to use two PSRAM devices to STM32's QuadSPI interface. Each PSRAM device has its own chip select line cs_b. How do we have such control with the _NCS line in a single-bank quadspi interface? Should we use two extra lines of GPIO separately (without _NCS) or logically linked with _NCS by external gates?

Thanks for help.

[Tesla DeLorean]

You don't mention which STM32 (several hundred variants now) you are using, and have no post history to review.

Most STM32 from L4+, F7 and H7 have two chip selects. I think they can be used independently or together. Allowing banking in parallel or consecutively. At least in direct access.

But yes, in the general sense you could OR the individual "Chip Select" GPIO with the NCS provided for the QSPI

Or you could find TWO mappings of the QSPI_BKx_NCS pin and switch the AF select between them, have an external pull-up, and switch one between GPIO/AF utilization.

[WQ_it]

We are going to use STM32WB5MMG. it has only one bank (one BK_NCS line) in QSPI to offer. Sorry for not mentioning it.

Before, in other MCUs, we didn't use the specific _CSB line from SPI peripherals, Instead, we always used GPIOs to be chip selects. This is the first project using STM32 and quad spi interface. We are just not very sure to its behavior.

We think using external OR logic of a GPIO and QSPI_BK_NCS would work. But, can we use GPIOs alone? It would save OR logic device. I would very appreciate the help on this matter.

[Tesla DeLorean]

Sorry, forum ate a response..

You'll have to proto-type and validate these yourself.

Very high probability GPIO OR NCS will work at first implementation.

The GPIO ONLY has some issues at a technical level. These memories have state machines rather than micro-controllers inside. The ability to modulate and resync via NCS is more likely than not to be important.