LoRa duty cycle on AT_slave example in STM32CubeExpansion_LRWAN_V2.0.0

[DPrie.1]

I'm testing this example code, and I'm having an issue with duty cycle.

Duty cycle is set to ON, so it must be compliant with the regulated duty cycle limits of 1%.

Actually I'm able to send messages everytime I receive the +EVT:SEND:CONFIRMED (every 5 seconds aprox.), so I think its not ok.

30/04/2021 09:15:25.444 [RX] - TX on freq 867300000 Hz at DR 0<CR><LF>
<CR><LF>
OK<CR><LF>
MAC txDone<CR><LF>
RX_1 on freq 867300000 Hz at DR 0<CR><LF>
MAC rxDone<CR><LF>
+EVT:SEND_CONFIRMED<CR><LF>
 
30/04/2021 09:15:29.874 [TX] - AT+SEND=12:1:abcdef0123456789abcdef<CR><LF>
 
30/04/2021 09:15:29.923 [RX] - TX on freq 868500000 Hz at DR 0<CR><LF>
<CR><LF>
OK<CR><LF>
MAC txDone<CR><LF>
RX_1 on freq 868500000 Hz at DR 0<CR><LF>
MAC rxDone<CR><LF>
+EVT:SEND_CONFIRMED<CR><LF>
 
30/04/2021 09:15:34.383 [TX] - AT+SEND=12:1:abcdef0123456789abcdef<CR><LF>
 
30/04/2021 09:15:34.434 [RX] - TX on freq 868300000 Hz at DR 0<CR><LF>
<CR><LF>
OK<CR><LF>
MAC txDone<CR><LF>
RX_1 on freq 868300000 Hz at DR 0<CR><LF>
MAC rxDone<CR><LF>
+EVT:SEND_CONFIRMED<CR><LF>
 
30/04/2021 09:15:38.796 [TX] - AT+SEND=12:1:abcdef0123456789abcdef<CR><LF>
 
30/04/2021 09:15:38.849 [RX] - TX on freq 867900000 Hz at DR 0<CR><LF>
<CR><LF>
OK<CR><LF>
MAC txDone<CR><LF>
RX_1 on freq 867900000 Hz at DR 0<CR><LF>
MAC rxDone<CR><LF>
+EVT:SEND_CONFIRMED<CR><LF>
 
30/04/2021 09:15:43.329 [TX] - AT+SEND=12:1:abcdef0123456789abcdef<CR><LF>
 
30/04/2021 09:15:43.376 [RX] - TX on freq 867300000 Hz at DR 0<CR><LF>
<CR><LF>
OK<CR><LF>
MAC txDone<CR><LF>
RX_1 on freq 867300000 Hz at DR 0<CR><LF>
MAC rxDone<CR><LF>
+EVT:SEND_CONFIRMED<CR><LF>

I think there is an issue on the new libraries, because the older example of AT_slave of STM32CubeExpansion_LRWAN_V1.3.1 is working ok with duty cycle, showing an AT_error when I can't send a message.

Any information about that?

Thank you very much.

[DPrie.1]

In order to make it work, I decreased the " #define DUTY_CYCLE_TIME_PERIOD       3600000" to 500000, and then I can send only every 100s aprox.

What's the meaning of this "period"? I dont understand what is the TimeCredits, and how can I set this value to have the 1% of ETSI regulations.

Any ST employee can help me? Thank you in advance

static uint16_t SetMaxTimeCredits( Band_t* band, bool joined, SysTime_t elapsedTimeSinceStartup )
{
 uint16_t dutyCycle = band->DCycle;
 uint8_t timePeriodFactor = 1;
 
 // Get the band duty cycle. If not joined, the function either returns the join duty cycle
 // or the band duty cycle, whichever is more restrictive.
 dutyCycle = GetDutyCycle( band, joined, elapsedTimeSinceStartup );
 
 if( joined == false )
 {
 // Apply a factor to increase the maximum time period of observation
 timePeriodFactor = dutyCycle / BACKOFF_DC_TIMER_PERIOD_FACTOR;
 }
 
 // Setup the maximum allowed credits
 band->MaxTimeCredits = DUTY_CYCLE_TIME_PERIOD * timePeriodFactor;
 
 // In case if it is the first time, update also the current
 // time credits
 if( band->LastBandUpdateTime == 0 )
 {
 band->TimeCredits = band->MaxTimeCredits;
 }
 
 return dutyCycle;
}

[Amel NASRI]

Hi @DPrie.1​ ,

DUTY_CYCLE_TIME_PERIOD is the duration in ms over which the duty cycle is considered, so here 3600000 ms = 1 hour.

The duty cycle management has changed in STM32CubeExpansion_LRWAN_V2.0.0; now the end-device is allowed to consume the credits for the 1 hour observation period.

Once all credits are consumed the duty-cycle is restricted. Over time it will gain credits again which will allow it to transmit again. It has not to wait necessarily for the full hour to expire to be able to transmit again.

The main reason to change the algorithm is to allow for more consecutive uplinks (up until it gets restricted).

You also have to take into account that the restriction depends on the number of enabled channels and sub-band specific duty-cycle. In particular if your network server enables extra channels in a sub-band with a duty-cycle less restrictive than 1 %, it can take long before being restricted by the duty cycle limit.

-Amel