load capacitance of recommended quartz for HSE lower than minimal load capacitor trimming

[HugoL]

The quartz used for HSE on the nulceo-wl55jc and on the reference design for stm32wl is NX2016SA 32MHz EXS00A-CS06465, which has a 10pF load capacitance (the BOM for reference design even mentions 8pF, but the quartz reference is actually 10pF).

The minimal value for SUBGHZ_HSEINTRIMR is 11.3pF, so higher than the load capacitance of recommended quartz.

Does it works thanks to the fact that parasitic capacitance is lower with internal bank capacitance? Still, in such a case, it seems that trimming is only possible in one direction?

Is 10pF really the recommended value or is it better to go for a quartz with a 12, 16 or 20pF load capacitance?

Thank you

[HugoL]

Any update on this issue ? Did I miss something?

Thank you

[HugoL]

I would have appreciated an answer. I will follow the reference design and hope for the best.

[Louis AUDOLY]

Hello HugoL,

Sorry for the late reply.

Actually there is no foot capacitor on the board, but there is bank capacitor inside the chip.

Two foot capacitor in parallel give Cload = C1C2/(C1+C2)

In our case C1=C2=Cfoot, so we have Cload = 1/2Cfoot

So the range of the capabanks is in the quartz specs of the nucleo

Hope it helps

Regards

[HugoL]

Hi Laudo,

Thank you for your clear answer. So indeed, I missed something... probably obvious for a HW designer, not so obvious for me.

Regards