Is it possible to have an ADC conversion rate >= one million samples per second while having the system clock low enough to put the system into low power sleep mode (<2Mhz)?

[JTrie.2]

Hello,

I have an inquiry about the capabilities of my STM32WB55CE microcontroller. Is it possible to have an ADC conversion rate >= one million samples per second while having the system clock low enough to put the system into low power sleep mode (<2Mhz)?

I've been using DMA to store conversions in a circular buffer, and I've been using the HAL library with CubeMX to initialize the ADC.

I've tried playing with sample and hold times as well as the ADC clock and the System Clock, however, it seems like if I want a 1Msps I need to keep the system clock over 16Mhz. If I try to set the System clock to be any lower, I get an ADC overrun error. This means that the DMA cannot keep up with the rate of conversions done by the ADC.

Are there any workarounds to this error that don't involve sacrificing the sampling rate or increasing power consumption?

[Remi QUINTIN]

No deep low power mode will enable such performance for the ADC.

Need to check whether the low power run mode can achieve it.

Note that an specific low-power mode is implemented for the ADC to allow very low consumption at low frequency... but not sure the performance is inline with what you want.

[Remi QUINTIN]

No be more accurate in my answer, the analog part of the ADC is switched off in deep low power modes.

The ADC is only active in sleep, low power sleep, low power run or run modes.

The frequency you need to use also depends on the resolution you are looking for.

For 6-bit resolution, the conversion needs 6.5 cycles to be completed. It is 12.5 cycles when the resolution is 12 bits.

So you can calculate the minimum frequency for your need for 1 Msamples.

[Remi QUINTIN]

For 12-bit resolution, you need 12.5 MHz for 1M samples/s. So 16 MHz is the correct value.