I want to use a part of SRAM2a of STM32WB50x from F/W of CPU1, what should I do?

[MNitt.1]

I want to use a part of the memory of SRAM2a with CPU1 (M4) with STM32WB50x. Is that possible?

(01) I changed the LENGTH of RAM_SHARD of the ld file to 6K and buffered 10KByte from 0x20031800 of SRAM2a, but when I received many packets of Mac802.15.4, the contents of the buffer were changed and the Wireless Stack changed. I feel like I'm doing it.

(02) I changed the IPCCDBA of Option Byte of SRAM2a from 0x0 to 0x2800 and changed the ORIGIN of RAM_SHARD of the ld file to 0x20032800, but the IPCC receive interrupt did not occur.

[Remi QUINTIN]

​SRAM2a is 32KB. So I would advise you to append your buffer on top of this RAM_SHARED area which was sized to 10KB.

Do not modify the size of this RAM_SHARED memory area.

Do not change the IPCCBDA offset either, though it should not have an impact but it points to the start of the information table filled by the M4 core and used by the M0+ core to determine where the intercommunication buffers are located. Some values may be hard coded somewhere in the FW.

[MNitt.1]

Thank you After monitoring the memory usage, the content will change between 0x20002800-0x20003FFF each time 802.15.4 is received. The F/W I created doesn't access this area, so I think it's used by the Wireless Stack. Is there something like this?