how do you enable communication between cpu1 and cpu2 in stm32wb55?
i have fuse 1.1.2 version and full_ble stack in the m0.
The option bytes are 0x1FFF8078=0x9E2BD000 and IPCCDBA = 0.
when i start the m0 ( bit 15 of PWR_CR4) I have that in the SRAM2B
20030000 : 24 00 03 20 00 00 00 00 00 00 00 00 00 00 00 00
20030010 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20030020 : 00 00 00 00 B9 56 46 A9 01 00 00 00 00 00 01 01
20030030 : 00 00 02 01 06 00 00 00 03 00 0F 01 26 00 00 00
20030040 : 00 00 00 00 00 00 00 00 00 00 00 00 95 69 1B 00
20030050 : 26 E1 80 00 96 04 00 00 00 00 00 00 00 00 00 00
this is correct. But when i try to send any request (example FUS_GET_STATE 2 times to start wireless stack) with ipcc the m0 didnt answer. I tried to enable ipcc for each cpu and enable it rx and tx for each but it doesnt work.
the bit 1 ( for channel 2 ) in IPCC_C1TOC2SR is stuck to 1 ( the cpu2 did not put that bit to 0)