How critical are the RF matching network values?

[Waller.George]

Hi all,

I am developing an application on the STM32WLE5CC based on the existing Nulceo boards for the JC part. First, the BoM provided for the JC reference is completely incorrect, it doesn't match the RF network design note, it's own schematic or the CC reference design. I fixed this by following the RF app note. However, my PCB still does not work (the code works on the Nucleo board) and I find the CC ref design different to the JC.

My question is, how important are the values for the RF matching network. If I just want something to work over the distance of the desk, would 20% be okay? Just to get an idea.

Also, can anyone recommend a good way of debugging why my PCB doesn't work. The schematic is correct (checked 100 times) and so are all the values according to the CC ref design. The code works on the Nucleo board so I know that isn't the issue.

Many thanks

[Bruno_ST]

Hello @Waller.George​ 

>My question is, how important are the values for the RF matching network. If I just want something to work over the distance of the desk, would 20% be okay? Just to get an idea

Got the info from my RF colleague that the max tolerances on small value is 5% (few ~pF) and on greater value 10% to meet best performance.

[Waller.George]

Thank you for the answer Bruno this is very helpful I our deployment.

The root cause of the issue we were experiencing was we fitted load capacitors onto the crystal generating the clock for the LoRa carrier frequency which are not needed as they are included in the MCU package. The capacitors pulled the crystal frequency low, making the carrier frequency out of spec.