Debugging STM32WB15CC-CM0+ core
Hi,
I am currently attempting to debug the secondary core (cortex-M0+) on the STM32WB15CC board, but I have encountered challenges in doing so. According to the documentation, the boot process is initiated by setting C2BOOT through the primary core (cortex-M4) to 1. However, I discovered that the debug interface is locked in CPU2, indicated by the DDS bit being set to 1.
It appears that unlocking the debug interface in CPU2 is not straightforward, as the documentation states:
"Debug access to the CPU2 is disabled, as indicated by the DDS field in the Secure Flash memory start address register (FLASH_SFR). The debugger has no access to the CPU2 and the secure peripherals and memory areas."
Can you please share any hint or assistance.
Grateful for the attention!
Gaya