Why do LTDC registers fluctuate between zero and programmed values?

[Chris Rice]

We are creating a display application using an STM32F7, using the LTDC and the DSI with the wrapper enabled. We program all DSI and LTDC registers, and perioidically write pixel data to the framebuffer and then refresh using (DSI->WCR |= DSI_WCR_LTDCEN.

This works fine, but I noticed in my STM IDE in the LTDC system peripheral viewer, the registers are mostly zero and occasionally flicker to the programmed values. I wrote some code to spit out the register values over UART and see the same behavior in the read values... they are mostly zeroes, and occasionally (after refresh?) the programmed values.

Why is this? Is this because it is being controlled by the DSI. Obviously this is something I should understand but can't find an explanation for it in the reference doc.

Thanks for any insights...

[h2obrain]

While playing with the STM32F769 board I noticed the same thing.

It seems to only happen, when I configure the DSI-host in adapted command mode.

To change ltdc settings like windowing, I need to do the following steps (found out via trial and error):

• disable the wrapper
• change settings
• do an immediate shadow register reload (RELOAD_IMR)
• wait for the RELOAD_IMR to be cleared
• enable the wrapper

It seems the shadow registers are rerouted by the dsi-wrapper behind the scene, but I could not find any documentation on this, or on how one is supposed to read/write those ltdc register.

I would also appreciate some insights on this.

[Tesla DeLorean]

Perhaps stop conflating peripheral registers with memory.

On many occasions you write to a different register than you are reading. You could be reading an active counter, not a latched value.

For displays presumably so you can adjust data that is already behind the active raster.

[h2obrain]

I do not understand, what you are trying to say. I could store the settings somewhere in memory of course, but the question was about why it is not possible in this case to read the configuration registers (I would expect such behavior to be documented in the reference manual).

Also, when I have errors in my configuration the ltdc_error_isr is called, but ltdc_isr reads some strange values in the reserved bits and 0 for the actual interrupts, which should never happen (or be prominently documented) in my opinion.

[h2obrain]

Turning off the DSI wrapper during the read seems to work..