stm32l4r5 - LTDC FIFO underrun error

[Franzi.Edo]

Dear All,

We are running a graphical application using LTDC and DSI on a STM32L4R9 discovery board. We refresh the display per portions with the DSI peripheral configured in adapted command mode. 

At the beginning of a portion refresh, we are reconfiguring the windows position and size in the LTDC (only layer 1 is used). The next portion refresh is started after the end of refresh interrupt from DSI.

During some refresh, the LTDC is generating a FIFO under run error. We did several tests with different pixel clocks, always with the same error.

Test conditions:

frame buffer of a portion is in internal RAM

Display size 454 x 454 (RGB888)

HCLK 120 MHz

PCLK1 120 MHz

PCLK2 120 MHz

PLLDSICLK 30 MHz

LTDCCLK tested from 3750 kHz to 15 MHz

How can we know if there is a congestion on the AHB bus which starve the LTDC FIFO? 

How can we troubleshot the LTDC underrun errors?

Is there a way to set some priorities on the internal buses or the LTDC peripheral?

Any idea to workaround this issue?

Thank you,

Best regards, Edo.

[waclawek.jan]

Read Checking display compatibility considering the memory bandwidth requirements chapter in AN4861.

The best option is to avoid bus conflicts entirely: keep the display buffer in SRAMx not used by any other busmaster (e.g. in SRAM3), and avoid writing to that SRAM while displaying is active - that includes accesses using DMA2D and GFXMMU too.

JW

[Franzi.Edo]

Hi Jan, thank you for your suggestions. I will try to reallocate the memories in my system in order to let the display buffer alone in the selected memory.

Stay tuned. Thank you

Edo