stm32f4 DCMI related proposed specification conflict

[armindavatgaran]

Posted on February 13, 2017 at 16:57

Hello

It is mentioned in the dcmi section of the stm32f4 electrical specification that the max pixel clock is 54MHz with 14 data lines which yields to 94.5MBps throughput, but the max throughput is said to be 54MBps in the dcmi section of both datasheet and reference manual.

#54 #94.5 #throughput #stm32f4-dcmi #confusion

[Tesla DeLorean]

Posted on February 13, 2017 at 17:08

I'd agree that the documentation doesn't really account for bytes/words in a coherent fashion.

From a practical sense the sustained rate is likely to be lower as you have to process and store the data. ie your ability to capture specific frames, vs streaming a continuous sequence of frames over a second or more.

[armindavatgaran]

Posted on February 16, 2017 at 16:18

Hello

As i inspected through some of stm32f7 datasheet, it is clarified in dcmi section that the throughput rate is 54MBps for 8 bits of data at 54MHz. but the conflict remains as it is said in electrical section that (as in stm32f4 datasheet):

Unless otherwise specified, the parameters given in

Table 120

for DCMI are derived

from tests performed under the ambient temperature, f

HCLK

frequency and V

DD

supply

voltage... .

If the tests are really done for 14bits of data at 54MHz, the throughput rate then must be 94.5MBps. the question is what was the DMA configuration under test condition? by ignoring the cpu ability to process this amount of data rate, is this throughput rate achievable by dcmi and dma together or not?

[Tesla DeLorean]

Posted on February 16, 2017 at 16:26

The DMA, and the memory behind it, would need to sustain 108 MBps

[armindavatgaran]

Posted on February 16, 2017 at 17:34

You are right, 4bits in every word is unusable but must be sent, So is it able or not?