Octo/Quad SPI RAM advice on graphical board

[pcu]

Hello,

To have a powerful graphical interface, you need a lot of RAM.

Can we use external RAM in Quad / Octo SPI for this?

The ST kits with screens often have flash in quad/octo SPI but the external RAM is always in parallel (except STM32L4R9I-EVAL).

I suppose there is a reason and the RAM in SPI would be a bottleneck?

Pierre

[Mon2]

I think you may be ok with QSPI mode use RAM but you will need to invest some quality R&D time.

Review the following and post your results:

https://touchgfx.zendesk.com/hc/en-us/articles/360020208091-Configuring-STM32F769I-DISCO

on how to use QSPI flash. Using the same methods, you may be ok to extend to use of external QSPI RAM. Keep your wiring short else you will face signal integrity issues.

[S.Ma]

More details on the application and type of graphicd.is needed. If the display has its own frame memory, then the time to update the frame will determine the max frame rate and animations.

Octospi means serial memory best addressed by incremental address

Remember tge read is easy, not the write. Octospi ram wouldn t be ideal.

The psram gives easy read write access. So it really depends.

[Tesla DeLorean]

Normally the QSPI NOR is there to hold graphic bitmaps, icons, etc.

Anything used for rendering or manipulation needs to be fast and provide the bandwidth required without bogging down the system.

Use 32-bit wide data buses where possible.

Do some basic computations based on screen size and frame rates. ​

[Andreas Bolsch]

QuadSPI (F4, F7): memory mapped mode is only possible for *read*, not for write, which defeats the use of RAM. Additionally, in memory mapped mode there is some sort of prefetch (although the RMs don't say anything precise) for *sequential* read, which makes it reasonable fast for code execution.

OctoSPI (L4+): memory mapped mode is possible for both read and write. Didn't try it yet, so I can't say anything substancial regarding performance. But I wouldn't expect to much. Mostly senquential read and write in large chunks won't be too bad, I guess, but true random access ...

[Tesla DeLorean]

Waiting on an STM32L4R9I-EVAL, supposed to have QuadSPI RAM on that.

The display resolutions supported on STM32 platforms are rather pedestrian, with bandwidth ceilings on the LTDC and DSI.