Memory scheme best compromise. QuadSPI or multiplexed Octospi

[Bob Bailey]

With limited pins, which would be best (fastest)? 2x Quad SPI (ram and flash), or multiplexed Octospi?  I'm in the planning stage of a project using the STM32H735.   What are the limitations of ChromART and TGFX relative to memory architecture? Any other pitfalls?

Thanks

Bob

[Alex - APMemory]

Hi,

I'm not sure how you want to handle your memory controller usage and if you mean using 2 independant memory controller using 2 quad SPI RAM in comparison to one OPI memory controller using one OPI RAM ? Unless your have 2 applications completly independant, I would say using only one device seems easier than two.

For info and help you to compared different option, APMemory IoT RAM are supporting following bandwitht

• 16Mb~128Mb QSPI SDR (6pins) up to 72MB/s @144MHz
• 128Mb QSPI DDR (7pins) up to 166MB/s at 166MHz
• 64Mb ~512Mb OPI (11pins) up to 400MB/s at 200Mhz

Regards

Alex

[Tesla DeLorean]

Putting RAM on QSPI is generally a head-ache. Access efficiencies come from continuous streams, not random access, mixed read/write.

The QSPI NOR Flash memory is cached, I'd recommend using the SOIC16W footprint devices as these are prolific, you can choose to populate one or two. Perhaps accommodate dual-die wiring options.

If using SOIC8 use large land patterns to accommodate parts of differing widths. Watch for annoying mix of ground pad geometries amongst different vendors.

You can't use direct access and memory-mapped concurrently.

You need to code external loaders for unique parts or pin combinations. https://github.com/cturvey/stm32extldr

NOR Flash is optimized for Read, and Erase/Write are SLOW.

A lot of the DISCO/EVAL boards have dual configurations, or single chip, dual die, review schematics.

Benchmark performance, you can try different clocking options, using one chip or both.

[Alex - APMemory]

RAM or NOR choice is depending of usage.

if you need a RAM for STM32H735, for frame bufering for example,, I'll suggest either OPI or QSPI DDR, upon BW and pin count

Alex