LTDC confused between multilayer and multibuffer

[frackers]

I have an STM32F769I talking OK from SDRAM via LTDC and DSI to a RAMless display (ILI9806E).

I'm trying to implement multiple buffers to allow writing to one whilst another is displaying to prevent the display breaking up. What I can't work out is which layer this multiple buffering should be carried out on or whether it even matters (0 or 1).

Another area of confusion is with HAL_DMA2D_ConfigLayer and whether the layer this is referring to is the same as the layer I have activated with __HAL_LTDC_LAYER_ENABLE or are they independent?

I thought I had is sussed when I implemented 3 buffers in separate SDRAM banks such that 1 was displaying via the LTDC CFBAR register, 1 was being filled by the application and the final buffer was copied from the 'active' one just before it is switched in the HAL_LTDC_LineEventCallback so it is ready to become the new active application buffer.

As it happens I get incomplete filling of the buffers somehow!!

I can't find enough detail in any of the examples in the F7 HAL, does anyone know of additional resources?

[cameronf]

I believe you want layer 0. I think the multiple layers in the LTDC peripheral are for having the LTDC pull from 2 different bitmap buffers in RAM and overlay them with alpha channels. The double/multiple buffering referred to in GFX is multiple buffers in RAM that take turns being read from by LTDC but always on layer 0 for the LTDC. I haven't looked into exactly how the LTDC peripheral works but this is my understanding.

If you already have it working with a single buffer on layer 0, you should just be able to enable double buffering and be good to go. You can break point in the code that assigns the frame buffer pointer to the LTDC to verify that it switches between the 2 buffers.

[frackers]

I'm making progress at last but still some questions about the fundamentals!!

In CubeMX I had defined 2 LTDC layers. This meant that layer 1 was sitting over the top of layer 0 and all my manipulations were on layer 0 where I couldn't see them reliably.

Confusion still reigns with the layer parameters for DMA2D. All the examples I've looked at use LTDC layer 0 but DMA2D layer 1. Makes no sense!

Does anyone who has actually used these IP blocks got any ideas?

[cameronf]

For DMA2D, the 2 layers are unrelated to the 2 layers for the LTDC. DMA2D layer 0 is the background layer and layer 1 is the foreground layer used during transfers. You can use both of them to blend 2 bitmaps or if you're not doing any blending and want to just copy an image from one source or do solid color fill you can use just the foreground layer (layer 1).

If you download the application template for the Discovery kit for that chip, the DMA2D driver included there is a good working reference (STM32F7DMA.cpp)

[cameronf]

I just realized, I made the assumption you were using touchgfx even though you didn't mention it which is why I've been referencing it.

Even if you're not using it the DMA2D driver they have for the disco kit works out of the box and should be a good working example if you want one.

[frackers]

SOLVED

The problem was the pixel clock was too high - SDRAM had enough bandwidth with just the LCD refresh but missed data when trying to interleave reads/writes.

Reducing the clock from 27 to 19.2MHz (frame rate down from 71Hz to 50Hz) has fixed the problem - no more jaggies on the screen when updating!!