Is there a way for DMA2D Register to Memory (A Fill Operation) to write in increments less than 32-bit?

[evan]

Using the 469/479 series. I'm using a CLUT based 8-bit pixel format, the DMA2D register to memory operation seems to only allow 32-bit sized transfers, is there a way that I'm missing to transfer in 8-bit increments? Thanks!

[berendi]

DMA2D output can't be CLUT based, only (A)RGB. So, only 16 or 32 bit output is supported. See the possible values of the OPFCCR register in the reference manual.

[evan]

"DMA2D output can't be CLUT based"

This seems slightly contrary to how the memory to memory transfer is documented (memory to memory only, no PFC), while the DMA2D transfers may not be CLUT based, it does seem to allow for 8-bit pixel formats, or rather fundamentally an 8-bit alignment . The reference manual lists L8 and A8 as possible values for DMA2D_FGCOLR, and perhaps more directly in the FGMAR (foreground memory address) register says:

"The address alignment must match the image format selected e.g. a 32-bit per pixel

format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-

bit per pixel format must be 8-bit aligned."

So my understanding based on reading the reference manual several times is that a copy can be 8-bit aligned, but a fill must be 32-bit aligned.

You mention the OPFCCR, but does that have an impact on the transfer if Pixel Format Conversion is not used?

Thanks for the input!

[berendi]

> a copy can be 8-bit aligned

Right. Unless it involves blending or PFC. But you've asked about filling.

> but a fill must be 32-bit aligned

I think 16 bit RGB565 output would work too.