FSMC timing calculation

[navintiwari08]

Posted on February 08, 2016 at 14:40

hello,

I want to interface SSD1289 lcd controller to stm32f103zet6 micro controller. I'm trying to understand the FSMC timing computations but to no avail. I referred to application note and found the following.

Could anybody please explain how these values are calculated. DATAST appears in equations for read and write. It will give two different values from these two different equations.

SSD1289 has following timing characteristics.

<<UNABLE TO POST IMAGE HERE, SO ATTACHING THOSE FILES>>

I really don't know how to go about this. Isn't the tcycle-read(1000 ns) in above sheet too much. can FSMC handle that?

I want to read and write to LCD. Kindly show me how to calculate the timing values. Thanks!

#ssd1289 #stemwin #fsmc #stm32f1

[waclawek.jan]

Posted on February 08, 2016 at 20:45

The FSMC chapter in RM is far from clear and error-free, so it might require some experimentation. Also, I don't quite believe in the controller's requirement for 500/500ns RD high/low - you might have troubles to achieve quite that, OTOH the controller might not quite require it. It might quite well be that a total cycle time of 1000ns would be sufficient, and that might be achievable, given DATST is 8 bits long and 1000ns at 72MHz is 72 HCLK cycles. The other half of read cycle might perhaps be achieved as a combination of ADDSET and BUSTURN (and/or ADDHLD in mode D).

Nonetheless, separate read and write timing implies FSMC_BCRx.EXTMOD set. Then you set timing parameters for read in FSMC_BTRx, and for write in FSMC_BWTRx.

JW

[navintiwari08]

Posted on February 09, 2016 at 06:28

Thanks JW! tried some values. Its working now. Although I still don't exactly know how to calculate them. Anyways, so long so good.