FSMC generating an extra write cycle

[ken239955_st]

Posted on July 25, 2016 at 17:06

I've developed code to drive an SSD1305 graphical LCD controller over an 8 bit parallel bus both via the FSMC & for comparison, bit banged. The FSMC generates 2 chip select pulses, but only puts data on the bus for the first one.

I'm using the peripheral libraries on an F407.

I've attached the FSMC setup code. I'll attach some scope traces next...

Regards

Ken

#fsmc #scope-traces-f407-lcd-tft #scope-traces-f407-lcd-tft

[ken239955_st]

Posted on July 25, 2016 at 17:09

Would it be possible to get the code for AN2790 - that doesn't seem to be on the web anywhere & that app note is the ''go to'' for all things LCD & FSMC, even though its for a slightly different LCD.

[Tesla DeLorean]

Posted on July 25, 2016 at 17:28

Wouldn't the code, or equivalent, be under the STM32F1 SPL (v3.5.0) under the Utilities directory containing the EVAL board support code?

[ken239955_st]

Posted on July 25, 2016 at 17:54

[ken239955_st]

Posted on July 25, 2016 at 17:57

________________

Attachments :

Scope_Sync_yellow_and_double_nCS_blue_FSMC.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1DX&d=%2Fa%2F0X0000000bjz%2FAOKTZlhIVy9SKGEAefnSleKykbBZIadNEbIvaYQVOrw&asPdf=false

[ken239955_st]

Posted on July 25, 2016 at 18:00

Yes it is, thanks. I'll ''go compare''!

[ken239955_st]

Posted on July 25, 2016 at 18:16

I've applied the differences in the example from the F10:

 p.FSMC_AddressSetupTime = 0x02;

  p.FSMC_AddressHoldTime = 0x00;

  p.FSMC_DataSetupTime = 0x05;

  p.FSMC_BusTurnAroundDuration = 0x00;

  p.FSMC_CLKDivision = 0x00;

  p.FSMC_DataLatency = 0x00;

  p.FSMC_AccessMode = FSMC_AccessMode_B;

&

FSMC_WriteBurst = FSMC_WriteBurst_Disable;

but to no avail.

Is there by any chance an errata on the bank that I'm using

.FSMC_Bank = FSMC_Bank1_NORSRAM1;

compared with FSMC_Bank1_NORSRAM2 in the worked example?

I have A16 driving my LCD's data/control# line which is tied into the addresses for FSMC_Bank1_NORSRAM1

i.e.

// 8 bit bus

#define LCD_REG (*(( volatile unsigned short * ) 0x60000000))

#define LCD_RAM (*(( volatile unsigned short * ) 0x60010000))

so I can't change that in software.

Regards

Ken

[waclawek.jan]

Posted on July 25, 2016 at 18:31

> // 8 bit bus

> #define LCD_REG (*(( volatile unsigned short * ) 0x60000000))

unsigned short doesn't sound 8-bit for me.

JW

[ken239955_st]

Posted on July 26, 2016 at 09:59

Thank you for spotting that, Jan - you were right! Unsigned short is 16 bit, and this was causing the transfer to be split into 2 cycles. It should have been ''unsigned char''. Now I have a sensible repeating pattern on my display!