DSI Clock Frequency

[DPfei.16]

Hello,

i have 25 MHz HSE Clock.

The DSI PLL settings are as follows: IDF 5, NDIV 80, ODF2

With these settings i measure an DSI clock of 100 MHz on the DSI_CKP pin.

But Cube says that the DSI clock is 200 MHz.

I use a STM32F769NI device with 2 DSI data lanes.

Do you have any idea?

BR

Daniel

[Tesla DeLorean]

They do on the surface look like appropriate numbers for a 200 MHz pixel clock.

As I recall the DSI clocks on both edges, effectively doubling the bandwidth, ie 100 MHz clock on pin equates to 200 Mbps on the wire.

I built a decoder for the LTDC/DSI clocks, will have to dig that up.

[DPfei.16]

Hi Clive,

thank you for your response!

I know DSI uses double data rate (DDR) and therefore data is transfered on the rising and the falling clock edge. This means when I have a DSI clock frequency of 200 MHz I have a bandwitdth of 400 Mbit/sec.

But I don't understand why the measured DSI clock frequency is only the half of the calculated DSI clock frequency.

[Tesla DeLorean]

The STM32's unit clocks at 200 MHz internally so it can generate data on both edges of the 100 MHz clock on the wire.

[DPfei.16]

Hi Clive,

many thanks for your help!

BR

Daniel