Question
Who enforces flash read protection and who actually blocks the read request at hardware level on STM32 ??
Hi,
I am working on flash memory protection mechanisms on STM32 microcontrollers (specifically STM32L476RG) and I have two closely related questions that I want to confirm at the hardware level.
I understand that:
- RDP (Readout Protection) levels are stored in the Option Bytes
- The Option Byte Loader (OBL) reads these values at every power-on reset, before any user code executes
- Under RDP1, external debugger access to flash is blocked but the CPU can still read its own flash normally
- Under RDP2, the debug port itself is permanently disabled
My question is: what specific hardware block is actually responsible for enforcing this protection? and blocking the read request to secure flash region ?
Specifically I want to confirm:
- Is this enforcement done purely in silicon/hardware, with no software component involved?
- Under RDP1, why does the CPU running normal user code still get real flash data, while an external SWD/JTAG debugger gets blocked — is this distinction made by the flash controller itself based on the bus master identity, or is it enforced differently?
I've read the STM32L4 reference manual (RM0351) sections on Flash and Option Bytes but wanted to confirm the architectural picture from someone with deeper hardware-level knowledge.