STM32H7 RNG clock configuration

[Gpeti]

I'm using for the first time the RNG of STM32H753. I have a "clock error" which means that rng_clk is too slow compared to HCLK.

The reference manual mentions the following:

 

Is it a problem to just disable the clock error detection since it seems that the level of entropy fits the statistical benchmark ?

Right now I disabled the clock error detection, kept rng_clk to the default value(hsi8_ck) and the bit DRDY is never set after I enable the RNG.

[TDK]

Disabling error detection because you're seeing errors is rarely the proper course of action.

Show your code where you set up the clock, or a readout of the registers which control it. It sounds like the clock is not what you think it is.

[Gpeti]

Well, the disabling of clock error detection is mentioned by STMicro in the ref manual and the RNG still seems to reach a good level of entropy and to work in this case (or I didn't understand the paragraph of the ref manual copied above).

Anyway I've switched rng_clk to another faster clock source and I don't have errors anymore.

I'm still curious to understand what my problem was.

No need to show my code, clocks are at maximum (HCLK 200MHz IIRC), rng_clk source was the default one ie. HSI