Hello @Keld and welcome to the community;
The VFBGA package dimensions are illustrated in DS14791 Rev 9 precisely section "6 Package information".
Regarding the comments on length equalization in our STM32N6570-DK and NUCLEO-N6570X0Q board schematics, the BGA package lengths mentioned in the comment likely refer to an older design that is not necessarily related to the STM32N6.
Here are the routing recommendations:
1- the die bumps to package balls substrate length is not released to customers as the package skew is considered negligible for xSPI frequencies. Therefore, they do not need to be taken into account.
2- The 50 mils specification can be extended to a matching length of 200 mils for all XSPI signals and that if the external memory is on the same PCB as the STM32N6, then the physical dimensions of the package can be neglected in the sizing.
3- Finally, as a recommendation, you can be in charge of the PCB design refer to the IBIS models containing the die IO + package models for xSPI signal integrity simulations and check to ensure results are within specifications.
The STM32N6 Ibis model files for all packages are available in the link below:
https://www.st.com/en/microcontrollers-microprocessors/stm32n6-series.html#cad-resources
Thank you.
Kaouthar
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