WWDG interrupt(EWI) is not getting while writing Flash

[SN_it]

Hi ,

I am in STM32L071CZ and using window WDG EWI to refresh the WDG counter to avoid RESET.

window = 127

Counter = 127

Prescaler 8

Enabling the EWI and reloading the wdg counter in the ISR to avoid the RESET by WWDG.

But while writing Flash it seems the WDG is resetting without generating interrupt (where counter reload has taken care to avoid RESET )and and flash write is also not complete.

Q1. While writing the Flash there can not be Interrupt? CPU can not jump to the ISR?

Q2.In my software CPU entering low power STOP mode - during STOP mode window wdg counter will keep running ?

Thanks.

[SN_it]

Anyone faced this issue? Any help?

[hs2]

If the ISR code is in the flash (bank) you’re erasing/writing it can’t be executed. It’s documented in your MCU reference manual that accesses to flash are stalled while erasing/writing. Both operations might take a while (see the docs).

So either you increase the WWDG timeout to cover the worst case (large sector erase I guess) or locate the WWDG ISR code in RAM as done for the low level flash routines.

[James Murray]

I faced this same problem. My solution was to execute the flash action from code in RAM. Then have a while loop waiting for the complete flag, in this loop I keep resetting the watchdog.

From other posts it is impossible to set the WWDG timeout long enough to wait for the flash action.

James