write TFT LCD through FSMC wrong !

[boomh1]

Posted on June 16, 2009 at 06:55

write TFT LCD through FSMC wrong !

[boomh1]

Posted on May 17, 2011 at 13:14

When I write a data (16bit) to the GRAM of a TFT LCD through the FSMC like this:

*(u16 *)(Bank1_SRAM4_ADDR ) = Para;

I found that the ''WR'' pin generated two negative pulse,but not one pulse, RS pin(A0) was low when the first ''WR'' pulse issued while high when the second ''WR'' pulse issued, so it wrote the wrong data to the GRAM. what caused this?

anyone can help me? some codes listed below:

#define Bank1_SRAM4_ADDR ((u32)0x6C000001)// for LCD control reg

#define Bank1_SRAM4_ADDR_RS ((u32)0x6C000000)// for LCD status reg

p.FSMC_AddressSetupTime = 1;

p.FSMC_AddressHoldTime = 0;

p.FSMC_DataSetupTime = 5;

p.FSMC_BusTurnAroundDuration = 5;

p.FSMC_CLKDivision = 0;

p.FSMC_DataLatency = 0;

p.FSMC_AccessMode = FSMC_AccessMode_B;

FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM4;

FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;

FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;

FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;

FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;

FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; //Low

FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;

FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;

FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;

FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;

FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

FSMC_NORSRAMInitStructure.FSMC_AsyncWait = FSMC_AsyncWait_Disable;

FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;

FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;

FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM4, ENABLE); /*Enable FSMC Bank1_SRAM4 Bank */

*(u16 *)(Bank1_SRAM4_ADDR ) = Para;

[boomh1]

Posted on May 17, 2011 at 13:14

The problem has been solved, change like this:

FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_ENABLE;

but I really wonder why the ''WR'' pulse presents 2 times when write data to extern sram through FSMC.

[boomh1]

Posted on May 17, 2011 at 13:14

Chris , you bet. para is (u16).thank u for your attention.

Boom.

[ccowdery9]

Posted on May 17, 2011 at 13:14

Presumably para is (u16) ?

Chris.

[pipiluxixi1]

Posted on May 17, 2011 at 13:14

FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;

Since the Data Width is 16bit, I think you should change

Bank1_SRAM4_ADDR ((u32)0x6C000001) to

Bank1_SRAM4_ADDR ((u32)0x6C000002)