Will the data be shifted right automatically when the data size is less than the slot size in SAI receiving?

[diverger]

The manual says the data received will be right aligned in the SAI_DR. Does this mean the data will be automatically shifted right if my data size less than the slot size. For example, a 24-bit data size with a 32 bit slot size? If so, how it treat the high bits shifted in? Padding with 0s?

Thanks.

[diverger]

I've test that. And it seems MCU will shift it right and simply padding zeros.