Why would I see different results writing data via the FMC while debugging with a breakpoint on the enable step compared to running without breakpoints? With the breakpoint, I get valid data.

[DBatc]

I'm using the FMC of a STM32H7 micro to communicate with an LCD, which has timing signals similar to a NOR SRAM. I have the MDMA configured to write 16-bit words out of a buffer to the FMC at the 0x60000000 address (bank 1). The MDMA is configured to transfer 8-bit values as 16-bit words to the FMC since the AXI bus is not supported with an 8-bit write to the FMC.

Near the start of the MDMA section of the reference manual (RM0455) is a note that there is no flow control when configured for memory-to-peripheral "the memory can also be replaced by a memory-mapped peripheral, which has no control over the MDMA flow." I tried to configure an interrupt to pace the data writes, but that appears to be for NAND flash configurations only. I see no apparent indications of "busy" status for the FMC while a write is in process, but I'm hoping there is something I can use for this purpose.

While it appears I may have a data overwrite condition, I do still see undesirable data (zero) on the bus when a breakpoint prevents any overwrites. Suggestions welcome on alternatives, but I am constrained on pin usage with my current hardware.

[DBatc]

Based on the post here titled "STM32H743II FMC + 8080 LCD spurious writes" and the reference to the caching feature noted in AN4839, it appears that data caching can affect memory bank 1. But swapping the memory bank out with one normally associated with SDRAM made a big difference.

Also interesting is that having a memory inspector open during debug can lead to reads of the memory, which was confusing at first.