Why there is a 1bit shift in MOSI with respect to the clock of spi in stm32f429zi discovery board?

[Vkuma.4]

I am using stm32f429zi discovery board.

When I am trying to use SPI peripheral, one bit shift in MOSI is observed with respect to Clock.

It is tested in all modes of SPI, still getting the same result in oscilloscope. We are not able to understand this behaviour of SPI.​

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[waclawek.jan]

Master? Slave? What is the content of SPI registers for the displayed picture, and what data are you trying to transfer?

If you've set SCK to highest OSPEEDR setting, switch to slower; if you've set it to slowest, switch to higher.

JW

[Paul1]

Clock Edge used...

• SPI ICs may clock in and out on different clock edges (rising, falling).
• If data out changed on clock rising edge, you likely want to clock in on clock falling edge, in centre of bit, after bit has stabilized (or even next rising edge).
• Many CPUs allow you to configure what edges to clock data in/out on so you can match to many ICs without needing inverters on clock signals.
• Check your STM32CubeMX settings for SPI for clock edge used.
• If you clock in and out on same edge you'll be clock in at data transition = may get garbage input.

Paul

[Vkuma.4]

Can you please explain or elaborate this?

[Tesla DeLorean]

Check clock phase settings, show initialization code.

[Vkuma.4]

We have tried with both clock phase rising and falling. The device configured is as master.

In this figure the data transferred is 1 bit i.e. 0x45.

The spi clock frequency set is 350 khz

​Here in this figure, we can there is shift of 1 bit. i.e. data transferred is 0xA2.

We have made TI mode disable still the waveform we are getting is likely to be the data transferred in TI mode as per datasheet.​

What could be the reason behind this data shift?​

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[waclawek.jan]

The delay between edges is suspicious, as if that picture would show waveforms from two different SPIs... which pins are we talking about? Are there other SPIs active on that board?

Prepare a minimal but complete compilable program exhibiting the problem and post.

JW

[Vangelis Fortounas]

Hello

for CPHA=1 and CPOL=1 the captured image does not have any bit shift. The output result is 0100 0101 (bit swapped) that is 0x45

Revise the use of pullups or pulldowns resistors (if exist) to fit with clock polarity and the other signals

check SPI registers if have the values that initialization code set.