What are the absolute levels of that signal (i.e. where's ground)? Which pin? How is it configured in GPIO? What is the output impedance of external circuit? Is the sampling time adequate? Are there other ADC inputs in use at the same moment (i.e. is the input multiplexed with other inputs)?
Thank you for the prompt reply. The signal on the capture is just under 30mV p-p. Frequency is 1 kHz. The input signal is biased at 1.5V (circuit and microcontroller supplies are 3V). The ADC is configured for differential inputs on pins 14 and 15. This is the only ADC channel (no muxing, etc.). The schematic of the ADC drive circuit is attached.
Here's the kicker: the distortion at the ADC inputs is signal-level dependent. Simply changing the input level to the ADC by 1mV introduces the distortion. For example, the screen cap shows the distortion with a 28 mVp-p input signal. If I reduce the signal level to 27 mVp-p, VOILA!, the distortion is gone. There is a range of signal level where the distortion manifests itself. Outside this range, either above or below, there is no distortion.
I have verified the signals coming out of the driver op-amps are clean. The distortion is only at the ADC inputs and when the signal amplitude is within a certain range.
I'm far from being expert on switched-capacitor ADCs, especially in differential mode, but I'd say the ADC's sampling capacitor may be left charged to quite different voltages (e.g. +VREF vs. -VREF, diferentially) at the end of the conversion, for input voltages above and below certain boundary (e.g. differential zero plusminus some offset). This then is charged from your 2k7/470pF impedance, how many, 1M times a second?
You may admit that this is some 6pF versus 2x470pF, but we are also talking millivolts versus volts.
Now regardless of whether this crazy theory is correct or (most probably) not, I personally would start by cutting down the series resistor and perhaps accordingly increase the parallel capacitor.
