Why is GPIO toggle output frequency half of expected timer frequency?

[NNagy.1]

I've been trying to configure a TIM6 to run at 48kHz, where APB1 is 108MHz, but because the APBDIV > 1, I used PSC = 449, and Period = 9:

216,000,000 / ((449+1)*(9+1)) = 48,000

And in my timer interrupt, I set a GPIO output pin to toggle. When I probe the pin, I get a frequency of 24kHz.

I found this closed question https://community.st.com/s/question/0D50X00009XkWG7/timer-3-clock-half-of-that-expected

that seems to indicate that the GPIO output frequency does not reflect the timer clock frequency.

But why is this the case, and why is the GPIO frequency half? (I've experienced this with other frequencies, prescalers, etc)

[TDK]

If you set the pin to toggle, it takes 2 updates for a full cycle, so the output frequency is half of the update frequency.

[waclawek.jan]

If TIM overflows at 48kHz, it means the interrupt happens every cca 20us (slightly more but that's not important here). You toggle the pin in that ISR, so it's low for cca 20us, high for another cca 20us so the total period is cca 40us, that corresponds to the 24kHz frequency you observe.

JW

[edit] Fixed us/ms mess, thanks MM

[MM..1]

Jan mix ms and us but yes all is defined how and wich interrupt on TIM you use

And in my timer interrupt

TIM dont have one interrupt , but around ten different , read PWM examples and usage CC...