Why is does the ADC stay on 2048 (12Bit)?

[RGmün.1]

Hello

Our STM32G4 is measuring a sinus-ADC value with offset. The offset is at VDDA/2.

Our ADC measurement shows a plateau at the offset, even, when the sinus signal is crossing the VDDA/2 (see attached picture).

The signal them self seems to be ok (measured by a KO).

Is there an ADC issue? Any hint, what this could be effected?

Settings from the ADC not ok?

thanks for your reply

[waclawek.jan]

This is consequence of inadequate (too high impedance) VDDA/VREF+ or even VSSA.

Read the 'G4-specific ADC appnote.

JW

[Andrea Canepa]

@Roland Gmünder​ Yes, this defect happened to me too. I was using the ADC's asynchronous clock and it was set to clock the ADC at 56.666 MHz (which would be lower than the maximum of 60 MHz with Vdd = 3.3V), but I had the flaw.

Furthermore, the same problem can be obtained on the NUCLEO-G474 board, so I believe that it should not have problems with impedance on the supplies VDDA/VREF+ ;)

I solved the problem by reducing the clock frequency to the ADC: I had to go down to 42.5 MHz to no longer have that step at 2048. Try it too.

I am curious to hear the response from STM employees.

Andrea.

[RGmün.1]

Hello both

thanks for your support.

I checked both solutions and both will bring me to the expected behavioral. :grinning_face:

The reduce from the clock is one solution, but we may need more speed.

The VDDA has a good impedance. The VREF+ has a "long" track to the first cap.. so I added there a 10n//1uF to the uC-pin and then the ADC value was also good!

Finally probably I'll implement both solutions. =) :thumbs_up:

So thanks for your quick and valuable support!!

Roland

[Andrea Canepa]

@Roland Gmünder​ 

"The VREF+ has a "long" track to the first cap"

How many millimeters is this "long distance" that you wrote?

I have a distance of about 5 millimeters from the pin (VddA or Vref +) and the pair of capacitors 100nF//4.7microFarad but I have the same problem as you.

Andrea

[RGmün.1]

Hey Andrea

The track from the voltage source to the microcontroller pin is about 20mm long. There is currently no cap between. I added a 10nF//1uF colse to the microcontroller.

Have you checked the Application Note?

https://www.st.com/resource/en/application_note/cd00211314-how-to-get-the-best-adc-accuracy-in-stm32-microcontrollers-stmicroelectronics.pdf

Section 4.2 -> Figure 20

• may use a 10nF//1uF
• have both pins (VREF+ and VDDA) decoupling capacitors?

Roland

[Andrea Canepa]

Hi Roland,

if you have 20mm track length without any capacitors then it is obvious that you may have this problem. But in my situation the pair of capacitors (100nF // 4.7uF) has the trace length of only 5mm, so I didn't expect to have such problems.

Also I do not understand why the defect is highlighted only around half scale (2048 units) and not in other points of the conversion.

Yes, I have seen that AN and I confirm that I have decoupling capacitors on both pins.

Andrea.

[waclawek.jan]

> Also I do not understand why the defect is highlighted only around half scale (2048 units) and not in other points of the conversion.

 The answer lies probably in the minute details of the ADC design. and might have to do something with the fact that the switched capacitor ADC revolves around VREF/2.

JW

[Nikita91]

It is because the switch from 0x7FF to 0x800 involve many bits, which produces a glitch on poorly decoupled power supplies.