Why clearing MOE in TIM1->BDTR in PWM mode stops triggering ADC1 IN STM32 Nulceo-64 for STM32F401 ? Used settings : TIM1: Trigger Event Selection_Output Compare(OC1REF) ADC1: External Trigger Conversion Source_ Timer 1 Capture Compare 1 Event

[Jeflet]

Hello everyone,

In the middle of an experiment i got stuck with an issue for which i hope somebody out here might know the solution.

I am using TIMER1 in PWM mode which is supposed be to continuously running in the background. Since triggering ADC using Timer1 update event is not possible in STM32F401, I used the following settings.

TIM1: Trigger Event Selection_Output Compare(OC1REF)

ADC1: External Trigger Conversion Source_ Timer 1 Capture Compare 1 Event

On sensing a particular value through ADC1 i need the Main output to be disable(i don't want to disable the timer) So i cleared the MOE bit in BDTR register.

But disabling the MOE bit actually stops ADC Triggering.

What could be the possible problem for ADC not getting a proper trigger when only the main output is disable and timer is still running ?

If this is not the proper way can ,what is the proper way to turn off output alone ?

[TDK]

Well, MOE disables the output, so I wouldn't expect output compare events to occur after that. Why do you need to disable it? I think you'll have to move it to another timer and trigger off of the update event if you need that functionality.

[Jeflet]

Thanks @TDK​ . In my project i had to keep ADC running in the background while the PWM output had to be disabled at different instances. While working with the NUCLEOf030r8 and CUBEIDE, ADC was properly triggered using TIM1 'update event' even when the MOE was disabled. But when i shifted to NUCLEOf401, ADC shows only the option to get triggered using Capture Compare Event and not the Timer 1 trigger out. Thanks for making it clear =)

[waclawek.jan]

The documentation is ehm substandard (read: plain wrong) in this point - the ADC is not triggered by a TIMx_CHy *event* (which would imply the same *event* which sets respective CCy flag in SR, triggers interrupts and DMA transfers); but by the TIMx_CHy *output*, which goes to GPIO (AF in GPIO doesn't need to be enabled for that CHy).

This question here comes up repeatedly, for perhaps all STM32 families, for years, e.g. this random selection

https://community.st.com/s/question/0D50X00009XkaxMSAR/timer4-trigger-for-adc

https://community.st.com/s/question/0D50X0000AIamaqSQB/trigger-adc-by-timer

ST, @Imen DAHMEN​ , can you please review RMs across families, and describe the *exact* source of ADC trigger. A detailed description of this ought to go also to interconnections chapters/appnotes (whichever applicable to given family), and I'd suggest adding one dedicated appnote (one of the "ADC dozens").

Thanks,

JW

PS. @Jeflet​ , next time please use terminology and numeric values based the RM; please don't use the terms and symbols randomly invented by Cube/CubeMX developers. This helps avoiding any further confusion.

[Jeflet]

@Community member​  Thanks a lot :)