While setting up the clock, if I set PLLM as 8 and PLLN as 360 , it gives same result as when I set PLLM as 4 and PLLN as 180, so what difference does it makes.

[SMand.2]

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[gbm]

If both sets of values lie within the allowed range (including the VCO max frequency) - there is not a big difference. Higher VCO freq will result in higher power consumption by PLL.

[Tesla DeLorean]

Depends where the sweet-spot is for the PLL comparison frequency. For the F2/F4 I think it was suggested in the 1-2 MHz region.

Also the VCO likely has a preferred operating range, ie 100 - 432 MHz.

Check the DM and RM

Typically you divide down the VCO frequency to get a square wave into the MCU