Skip to main content
Micael
Associate
December 9, 2022
Solved

While sending data on to USART1, I always get FEIF DMA errors. Why?

So I am setting up the DMA for USART1 tx on a STM32F4 on each transfer, and busy wait for it to be done (no interrupt) by polling TC.

 DMA2_Stream7->NDTR = len;
 DMA2_Stream7->PAR = (uint32_t)&(USART1->DR);
 DMA2_Stream7->M0AR = (uint32_t)str;
 DMA2_Stream7->FCR |= DMA_SxFCR_DMDIS;
 
 DMA2_Stream7->CR = (0x4 << DMA_SxCR_CHSEL_Pos) | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PL_1 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_1;
 
 USART1->CR3 |= USART_CR3_DMAT;
 USART1->SR &= ~USART_SR_TC;
 
 DMA2_Stream7->CR |= DMA_SxCR_EN;

First I ran without FIFO, (Direct mode), but that gave also FEIF and lost tx data. After enabling the FIFO, all data seems to be sent, but I still get the FEIF after each tx block.

I tried to reduce the baud rate down to 115200, but I still get the FEIF error...

Even if I only send 4 bytes, I get the FEIF, so I figure I must have configured something wrong.

I get TCIF on each send, and I think everything is actually sent fine.

Any help appreciated!

This topic has been closed for replies.
waclawek.jan
waclawek.janBest answer
Super User
December 9, 2022

Enable the DMA stream (set DMA_CR.EN) *before* you enable the DMA on peripheral (USART1_CR3.DMAT).

Read AN4031 4.3 Software sequence to enable DMA

JW

2 replies

waclawek.jan
waclawek.janBest answer
Super User
December 9, 2022

Enable the DMA stream (set DMA_CR.EN) *before* you enable the DMA on peripheral (USART1_CR3.DMAT).

Read AN4031 4.3 Software sequence to enable DMA

JW

Micael
MicaelAuthor
Associate
December 9, 2022

Wow, thanks a lot!

I clearly must be blind, or have some kind of deficiency ; I have read AN4031 several times without seeing that part. :grinning_face:

Now it works just as it is supposed to.

Cheers,

Micael