Which register selects the clock input to a STM32F303K8

[Randy Nelson]

Posted on February 16, 2018 at 19:22

The clock diagram in RM0316 for the 32F303K8 indicates a clock selection mux off the APBx prescalers. I've searched the registers and cannot find the register used to select one of 4 clock inputs. The 4 possible inputs are the LSE, HSI, SYSCLK, or the clock off the APBx prescaler. The outpu tis to the usuart.

Can someone point me to the register. 

Thanks...

Randy

[Randy Nelson]

Posted on February 16, 2018 at 19:32

Sorry missed indicating the whole point. I'm trying to select the input clock for the Usuart1 and/or Usuart(2..5).

Randy

[Tesla DeLorean]

Posted on February 16, 2018 at 19:43

RCC_CFGR3

[Tesla DeLorean]

Posted on February 16, 2018 at 19:34

http://www.st.com/content/ccc/resource/technical/document/reference_manual/4a/19/6e/18/9d/92/43/32/DM00043574.pdf/files/DM00043574.pdf/jcr:content/translations/en.DM00043574.pdf

 

SW bits of RCC_CFGR

The USART clock typically depend on the specific APB to which they are attached. ie USART1 on APB2 (fast bus), see RCC_APB2ENR

[Randy Nelson]

Posted on February 16, 2018 at 19:43

Clive,

I understand what you are saying but 'Figure 10. Clock tree' indicates the AHB drives both the APB1 and APB2 which gens PCLK1 and PCLK2. There is a 4-to-1 mux that can select as an input to the USUART either PCLK(1or2) or SYSCLK or HSI or LSE.

The RCC_CFGR->SW only selects:

00:HSI

01:HSE

10:PLL

11:not allowed

These signals names do not match. 

Randy

[Tesla DeLorean]

Posted on February 16, 2018 at 19:44

Sorry took me a while to dig through, and see second post

For the peripheral level muxing...

9.4.13 Clock configuration register 3 (RCC_CFGR3)