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tjdyhdsfeadgstdj
Associate II
October 8, 2023
Solved

Where is it documented that STM32H7 can only read memory mapped QUAD-SPI RAM?

  • October 8, 2023
  • 3 replies
  • 6098 views

I'm considering using a QSPI RAM to expand the RAM of an STM32H7 device (not FLASH).

If possible, I'd like to use memory mapped mode. However, when I was doing research on this, I ran across a bunch of posts saying that memory mapped mode for QUAD-SPI RAM is read-only.

For example, see this post: https://community.st.com/t5/stm32-mcus-products/is-it-possible-to-use-serial-sram-qspi-with-the-stm32h743/td-p/262301

Where is the documentation that states this? I looked through the datasheet and reference manual and see no mention of this. Do STM32H5 devices have this same limitation?

This topic has been closed for replies.
Best answer by KDJEM.1

Hello @tjdyhdsfeadgstdj ,

It is mentioned in AN4760 Section 3.3.3 Memory-mapped mode that, for Quad-SPI interface, the Memory-mapped mode is used in below cases:
• For reading operations.
• To use external Quad-SPI Flash memory like an internal memory, so any AHB master can read data autonomously.
• For code execution from external Quad-SPI Flash memory

And for Octo-SPI and Hexadeca-SPI interfaces, it is mentioned in AN5050 section 3.3.3 Memory-mapped mode, the Memory-mapped mode is used in the cases below:
• read and write operations
• to use the external memory device exactly like an internal memory (so that any AHB/AXI master can access it autonomously)
• for code execution from an external memory device.

I recommend  you to refer to Table 1. Applicable products in both applications notes.

The STM32H5 have an Octo-SPI interface, so read and write operations are supported in memory mapped mode. I advise when you configure the OCTOSPI interface to check the OCTOSPI errata cases.  

Thank you for your contribution in STCommunity :).

Kaouthar

3 replies

Andreas Bolsch
Andreas Bolsch
Lead III
October 9, 2023

Depends on the peripheral: QSPI interface supports only memory mapped read, OCTOSPI memory mapped read and write (but see errata!). Some H7 have QSPI, others (newer) OCTOSPI.

KDJEM.1
KDJEM.1Best answer
Technical Moderator
October 9, 2023

Hello @tjdyhdsfeadgstdj ,

It is mentioned in AN4760 Section 3.3.3 Memory-mapped mode that, for Quad-SPI interface, the Memory-mapped mode is used in below cases:
• For reading operations.
• To use external Quad-SPI Flash memory like an internal memory, so any AHB master can read data autonomously.
• For code execution from external Quad-SPI Flash memory

And for Octo-SPI and Hexadeca-SPI interfaces, it is mentioned in AN5050 section 3.3.3 Memory-mapped mode, the Memory-mapped mode is used in the cases below:
• read and write operations
• to use the external memory device exactly like an internal memory (so that any AHB/AXI master can access it autonomously)
• for code execution from an external memory device.

I recommend  you to refer to Table 1. Applicable products in both applications notes.

The STM32H5 have an Octo-SPI interface, so read and write operations are supported in memory mapped mode. I advise when you configure the OCTOSPI interface to check the OCTOSPI errata cases.  

Thank you for your contribution in STCommunity :).

Kaouthar

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T
tjdyhdsfeadgstdjAuthor
Associate II
October 14, 2023

Thanks, do you know if the OCTO-SPI in QSPI mode can also write to memory mapped RAM? (That is using a QSPI memory not an OCTO-SPI memory).

Andreas Bolsch
Andreas Bolsch
Lead III
October 14, 2023

Whether memory mapped write is supported is a question of the interface, not of the memory. So OCTOSPI *interface* allows memory mapped write, (in the first instance) regardless of the memory chip and mode (1-line, ... 8-line).

BTW: Memory mapped write makes rather little sense for flash memory, as these allow writes only after a write enable and only page-wise. So the memory mapped write is *intended* for RAM (or FRAM).

    Alex - APMemory
    Alex - APMemory
    Associate II
    October 14, 2023

    Hi, 

    To reply shortly to your question: based on STM32 currently available, STM32H7 won't support memory mapped write for QSPI SDR RAM (Alternative could be QSPI DDR or OPI), STM32H5 is supporting QSPI RAM full spec (https://eu.mouser.com/c/semiconductors/memory-ics/dram/?q=QSPI&m=AP%20Memory%20Technology)

     

    As a more general comment, there are a couple of different cases

    - STM32 which have only QSPI NOR memory controller. Memory Mapped Write function is not implemented. It can support QSPI SDR RAM (all APS1604M-3SQR, APS1604M-SQR APS6404L-3SQR, APS6404L-SQR, APS12804O-SQRH)

    -   STM32 which have Octal/QSPI memory controller, supporting Octal and QSPI DDR full spec, but still have a limitation for QSPI SDR. This applies to STM32H7Ax/Bx and STM32H72x/3x. Recommendation to use OPI RAM such as APS6408L-OBM, APS6408L-3OBM, APS12808L-3OBM, APS12808L-OBM, APS12808O-OBR, APS256XX-OB9, APS512XX-OB9.

    - STM32 which have Hexa/Octal/QSPI memory controller which support all device full spec. This applies to all new MCU coming, including  STM32L4P, STM32L5, STM32H5, STM32U5, ....Any IOT RAM can be used from 16Mb up to 512Mb, 6pins QSPI SDR, 7 pins QSPI DDR, 11pins OPI, 20 pins HPI, supporting up to 1GB/s in wide range of package such as SOP8/USON8, BGA24 and WLCSP.  IoT RAM is the most effective memory solution, key attributes such as pin count, power, space saving, simplicity of design and competitiveness  (https://eu.mouser.com/c/?tradename=APMemory)

    - Overview in below table:

    AlexAPMemory_0-1697271583977.png

    https://www.st.com/en/partner-products-and-services/iot-ram-opi-psram.html

    https://www.st.com/en/partner-products-and-services/iot-ram-hpi-opi-psram.html

    https://www.st.com/en/partner-products-and-services/iot-ram-spi-qspi-psram.html

    Alex

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