Where does the ''Frequency(PCLK2)= 3�8×Frequency(SDIO_CK)'' limitation for STM32F103 come from?

[Moritz M]

Posted on October 02, 2012 at 19:33

Hi,

does anybody know why there is this limitation (stated in RM0008)? 

(For the F4xxx the PCLK2-frequency has to be greater or equal)

So my next question is: what happens if I increase my PCLK2-frequency?

Thanks,

Moritz

#stm32f103-sdio-pclk

[elaroussi]

Posted on February 17, 2014 at 12:36

if I increase your PCLK2-frequency,the ADC can lost his accuracy.coz the PCLK2 is the APB2 clock which is (72MHZ). so 

Running the ADC overspeed is possible but I would expect accuracy to suffer.

[aaron2399]

Posted on January 12, 2016 at 01:04

For the first question, check the errata. I don't know where the errata sheet for STM32F103 is, but the sheet for STM32F40/1x has a section 2.11.6 ''No underrun detection with wrong data transmission'' that lists a similar restriction, saying that underrun errors may be missed if the restriction is not met.

http://www.st.com/web/en/resource/technical/document/errata_sheet/DM00037591.pdf

Conclusion: if the F103 family has the same issue and you don't meet the restriction, then you may have SDIO failures (read failures in my experience) that are happily returned as if nothing bad happened.

[Tesla DeLorean]

Posted on January 12, 2016 at 01:13

Medium Density

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/errata_sheet/CD00190234.pdf

High Density

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/errata_sheet/CD00197763.pdf