Where can I find the ADC input impedance of STM32H743 in differential and single-ended configurations?

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[Uwe Bonnes]

For the STM32H7 datasheet the R(AIN) formula given in the other STM32 ADC datasheet section is missing. You can apply it for the H7

The datasheet also doesn't have the sampling switch resistance value which is required by the formula.

Is it the same for both differential and single-ended inputs?

I suppose only somebody from ST can answer this question. Is there any way to elevate this question to them?

[Singh.Harjit]

​Bumping this up because the current situation has some serious problems.

Issue #1: BOOST bit definition missing in ADC_CR

• Datasheet DS12110, revision 6, Table 184, calls out BOOST as two bits.
• Reference manual RM0433, revision 6, 24.6.3 ADC control register ADC_CR, calls out BOOST at one bit.

From reading stm32h743xx.h, bit 9 of ADC_CR should be BOOST1 and bit 8 should be BOOST0

Issue #2: Radc not specified in data sheet

• Datasheet DS12110, revision 6 is still missing Radc.
• Figure 41 shows RADC and the footnote says it is in Table 87. Unfortunately, it isn't.
• Figure 93 shows RADC and the footnote says it is in Table 184. Unfortunately, it isn't.

Issue #3: Very convoluted to determine how to drive and configure ADC slow channels

• Table 184, page 278 says: Sampling rate for Slow channels (6) is 1.0MSps.
• Table 184, page 279 says: tS                Sampling time       1.5 to 810.5     1/fADC
• Table 184, page 279 says: tCONV       total conversion time (including sampling time)      ts + 0.5 + N/2 where N = conversion resolution
• Footnote 6 says: Slow channel performance is limited to 1 Msps whatever fADC value.

Table 185 calls out the minimum sampling time for a few source impedances (RAIN). Since this is sampling time, this should correspond to tS. However, none of the RAIN values in Table 185 match the RAIN values in Table 184 on the top of page 279!

Looking at the fs data for the direct and fast channels  in Table 184 on page 278, I am able to confirm that fs is defined calculated as: fs = fADC / tCONV

This says that for a 14 bit conversion, with an fADC of 36MHz, the sampling time has to be 1us - (0.5 + 14/2)/36MHz = 792ns. Since fADC is 36MHz, this is 28.5 clock cycles. From the reference manual, ADC_SMPR1, the closest sample time selection is 32.5 clock cycles. If I look up 792 ohms for RAIN in Table 185 of the datasheet, there is no entry for 14 bits.

If we used an fADC of 10MHz, the sampling time has to be 1us - (0.5 +14/2)/36MHz = 250ns. Since fADC is 10MHz, this is 2.5 clock cycles. From the reference manual, ADC_SMPR1, this matches one of the sample time selection values.

[Robmar]

And here we are, 5-years later, and still no answer!

[AScha.3]

Yes, so: 5-years later, everybody found its answer - or nobody cares of the 6pF switched to IN , or +IN and -IN .

+ You seen, what i wrote about the input "impedance" of this kind of ADC.

...as from rm :  the sampling cap /input is just switched to +in / -in , instead of +in /vssa :

Thats all.

[MasterT]

R-in = 1 / ( 2 * PI() * C * F ),

where PI() - math constant 3.14...,

C - sampling & hold ADC capacitance provided in DS,

and F - sampling rate in Hz.

[Robmar]

So assuming the below mentioned 6pF input capacitance on the H743 ADC inputs, and a 192 KHz sampling rate:-

R-in = 1 / (2Pi * 6pF * 192k) = 138 ohms

Would that be correct?

[MasterT]

No.

pF means 10^-12.

kHz : 10^+3.

[Robmar]

Let me revise:-

 

R-in = 1 / (2Pi * 6pF * 192k) = 138k ohms

dropped the K!

 

[Robmar]

I have been testing the ADC input impedance of the STM32H743 and have observed the discrepancy between DC and AC impedance measurements.

DC Measurement:

Using a bias resistor method, I measured a DC input impedance of ~709kΩ, derived from a 22kΩ bias resistor dropping 0.49V off a 1.61V reference voltage, indicating a 2.2µA bias current.

AC Impedance Expectation:

For an ADC sampling rate of 192kHz and a sampling capacitance of 6pF, the expected AC impedance should follow:

Rin = 1 / (2π × fADC × CADC)

Substituting the values:

Rin = 1 / (2π × 192kHz × 6pF) ≈ 138kΩ

This suggests that while the AC impedance could be 138kΩ, the DC impedance is significantly higher at 709kΩ.

Clarifications Needed:

1. Is this discrepancy expected? Does the ADC input exhibit different impedance characteristics at DC versus AC due to internal switching behavior?

2. How does bias current influence ADC performance? Are there known effects of steady-state bias currents on charge transfer dynamics?

3. What is the recommended bias current for optimal ADC operation at 192/384 KHz sampling rates? Should biasing conditions be adjusted to ensure accurate sampling behavior?

4. Are there recommended methods to experimentally verify the true AC impedance seen by the ADC input?

I would greatly appreciate any insights or guidance on these points.

[AScha.3]

> Is this discrepancy expected? Does the ADC input exhibit different impedance characteristics at DC versus AC due to internal switching behavior?

Hi Rob ,

you didnt answer to my post, but ask again (what i cannot understand ),

just tell me, whats the problem:

- you dont understand, how this kind of ADC is working , and what side effects it has ?

- you want detailed precise data about the caps and switches in the chip design , to do...what ?

- you dont accept the recommended input impedance (from ds, rm or ANxxx ) for the ADC ?

[Robmar]

Thank you for your response. Let me clarify my concerns:

• I understand how this type of ADC works, but I am investigating whether the difference between DC and AC impedance is expected behavior due to internal ADC switching dynamics.

• I am not requesting chip design details, but rather an explanation of whether this impedance discrepancy aligns with typical ADC behavior.

• I acknowledge the recommended ADC input impedance from the datasheet, but my real-world measurements show a different behavior, which I would like to understand.

The ultimate aim of my inquiry is to determine whether my design could be improved to enhance sensitivity to weak signals or reduce noise. If internal ADC effects influence input impedance differently at DC versus AC, this could impact front-end signal conditioning.