When SPI in Mode 3 is there a way to set the SCK or clock signal high before the first SPI transaction?

[KiptonM]

The L6474 uses SPI in MODE 3 where CPOL = 1 and CPHA = 1

My logic analyzer is saying that having the SCK low when the CS is pulled low or enabled the idle state of the CLK (a.k.a. SCK) is not correct for MODE 3. After the first transaction the SCK stays high as expected.

It does not appear there is a way to set the line to default high at startup.

Maybe I just do not know how to do it.

[waclawek.jan]

Which STM32?

I don't know how do you handle CS, but it should have nothing to do with it.

Try simply set up the GPIOs, set the SPI clock in RCC, set the two bits which set CPOL and CPHA and set CEN and then just infinite loop. This is simple enough so that you really don't need Cube/HAL for this - you can even do it without writing code, just clicking in the registers view in debugger.

Still SCK low?

JW

[KiptonM]

This is for the STM32L443CC but I doubt if it is an issue for a particular processor.

I handle CS outside of the HAL.

For example

#define L6474_CS_H L6474_CS_GPIO_Port->BSRR |= L6474_CS_Pin
#define L6474_CS_L L6474_CS_GPIO_Port->BSRR |= (uint32_t) L6474_CS_Pin << 16
 
static inline void delayGT800ns(void)
{
	__NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); __NOP(); // 10 
	__NOP(); // this is 906 ns delay must be > 800 ns some safety. (64 MHz system clock)
}
 
// this is the code snippet to read a parameter from the L6474 using SPI
 
	L6474_CS_L;
	HAL_SPI_Transmit(&hspi1, &parm, 1, SPI_TIMEOUT);
	L6474_CS_H;
 
	for (i=0;i<number_bytes_returned;i++)
	{
		delayGT800ns();
		L6474_CS_L;
		HAL_SPI_TransmitReceive(&hspi1, &tx_data.byte[i+1], &rx_data.byte[number_bytes_returned-i-1], 1,SPI_TIMEOUT);
		L6474_CS_H;
	}

You said:

"Try simply set up the GPIOs, set the SPI clock in RCC, set the two bits which set CPOL and CPHA and set CEN and then just infinite loop. This is simple enough so that you really don't need Cube/HAL for this - you can even do it without writing code, just clicking in the registers view in debugger.

 

Still SCK low?"

Sorry I may be a little slow.

The SYSCLK is 64MHz so I have to divide by 16 to get 4 MHz, as the L6474 SPI must be <= 5 MHz. I am a little confused where you say set the SPI clock in the RCC. I am looking at the RCC and do not see how to set it in the RCC. It is in the SPI. That is a little confusing to me.

I know how to set the bits for CPOL and CPHA, and CEN.

I do not know what you mean by infinite loop. I have to process bytes and do other things. I am not using an OS, but writing a simple application.

The L6494 needs the Chip Enable to go high for 800 ns after each byte (read or write), which kills the efficiency of the SPI bus.

Yes, I could not use the HAL, and I may switch because of how long it is between bytes because of the HAL bloated software,

Thanks for responding.

[KiptonM]

I do not know if this is the best answer, but I decided to write to the spi without lowering the CS pin.

The write left the SCK high, and everybody is happy when I go to actually read parameters, SCK s not left in an invalid state.

[waclawek.jan]

> everybody is happy

That's what counts, I guess :)

JW

[KiptonM]

Yes, but it feels ugly.