When one does ADC oversampling, what should be the sampling time?? Higher sampling time or lower sampling time will give better results??

[STee.3]

i am working on ADC oversampling using STM32 nucleo board. I have increased 2 bits by using appropriate oversampling ratio and bit shifting. But when i used lower sampling time i observed less % error between expected v/s measured ADC count then higher sampling time. May I know the reason for such behaviour?

[raptorhal2]

To be precise, is your "sampling time" the time between conversions, or the number of ADC clock cycles charging up the sample and hold capacitor before the ADC starts conversion ?

If it is the latter, the results are contrary to expectations, so describe the signal source.

[STee.3]

sampling time => number of ADC clock cycles. eg 5 cycles or 391 cycles.

Is it anything to do with oversampling??

[Piranha]

No. Oversampling just repeats the whole conversion of each channel multiple times, sums the converted values and at the end optionally divides the sum by right-shifting bits.

[S.Ma]

First characterize the input analog signal going to ADC.

Its input impedence, its frequency spectrum, max slew rate, noise level.

From this, you can deduct which strategy is best.

The sample and hold time expose the Switch+Sampling Cap as a time limited RC connection to the pin (usually around 2kOhm and maybe 3 pF). During the sample and hold time, the electrical charges from outside are accrued/stored in the sample and hold capacitor. For the internal signals such as VTemp or Vref, this time should be long enough, of the ADC converted value will seems too low from expectations.

Sampling longer charges and noise average for a specific amount of time.

Oversampling is the brute force blind way to do multiple ADC conversion and average the digital converted values. The previous way average in the analog domain over a certain time.