When exactly does SPI TXE get set in an F730

[GLero.1]

I am trying to change from using a Timer PWM controlled outgoing bit stream to an SPI controlled outgoing bit stream. It would be very nice to output a 32-bit word in one shot using the 4-byte FIFO at each TXE interrupt, but the RM seems to indicate TXE gets set when the FIFO is HALF empty and not when the FIFO is actually EMPTY (if so, who's stupid idea was that?!!)

If TXE is set when it is empty, I can stuff the fifo with 4-bytes at every interrupt. If TXE is set when the fifo is half-empty, now I have to interrupt twice to stuff the open end of the fifo with 2-bytes AND I have to keep track of which 2-bytes of each 4 I have already put into the fifo making coding that much more complicated.

So before starting to code, I need to know exactly which way TXE is being handled.

Thanks

[TDK]

Per the RM, TXE is triggered when the 32-bit TXFIFO is half-full or less.

 

> if so, who's stupid idea was that?!!)

Triggering before it's empty gives the mcu some time to populate the FIFO before it runs out. At higher clock rates, this can increase throughput.

If you're concerned about efficiency, DMA is a much better option.

[TDK]

Actually, looking more into it, the RM says three different things about this. I suspect what I wrote originally is correct, but I didn't check.

The excerpt in the original reply says TXE is triggered when the TXFIFO is less than half full.

This excerpt says TXE is triggered when half-full or less:

 

This one says it's only cleared when TXFIFO is full:

[waclawek.jan]

So it has some hysteresis.

Master Tx is synchronous, so the problem can be circumvented simply by ignoring TXE and using a timer.

JW

[GLero.1]

This would be a kludgy workaround for a bad design. Doing this means having to chain the "TXHE" signal event to start a timer set up to interrupt when it THINKS the SPI fifo is empty. Bad design.

If the designers wanted a TXHE signal then they should have called it that and also put in a true TXE signal.