When do we need to call Clean and Invalidate D Cache?

[Dat Tran]

Hi everybody, this maybe a very simple question but it is complex to me.

Are they only needed between DMA and Memory?

If we have few buffers but they are same RAM, do we need to clean/invalidate before copy or read?

If a buffer is located in uncache (by MPU), do we need to Clean and Invalidate D Cache before read/write?

Thank for the help!

[Tesla DeLorean]

Depends on the STM32 in question.

One does need to be careful with the Invalidate DCache, as it will kill things in progress.

Watch also the alignment and variables/structures that abut the sections you are touching.

DMA and other bus masters, like the M4 on the Dual core H7

[Dat Tran]

Thanks.

We are using STM32H7, single core, some buffers are located on SRAM1, 2,3 and AXI SRAM and they need to be transferred together.

[Pavel A.]

As usual with DMA: when the external device writes to the memory, you INVALIDATE the cache on the area, this means you discard anything that could come to the cache from the local side and accept the actual data in the RAM.

If external party reads the memory, you FLUSH the cache. This is called "Clean" in ARM documentation.

Flush ensures that all data written by the CPU arrives all way down to the memory and is available to the other party.

Even if the memory in question is not cached (so flush and invalidate operations do not apply) you may need to use memory barriers (DSB, DMB) after writing to memory mapped registers. Especially those related to interrupts.

-- pa

[Tesla DeLorean]

>>If a buffer is located in uncache (by MPU), do we need to Clean and Invalidate D Cache before read/write?

Depend on the nature of the read/write. If the CPU is writing you need to ensure that completes, as the write buffers defer the operation.

You'd minimally need some fencing instructions.

The Clean DCache by Address function will flush properly for a write. I personally would keep the SRAMs cached, and explicitly deal with the cohenerency

[Dat Tran]

Thank you a lot for helpful answer above! a little bit more :))

Let say we have 2 buffer on SRAM1 and SRAM2, and both of them are cached.

1. When we need to read/write between these two buffer, just read do memcpy, don't we care about invalidate / clean?
2. The address need to be aligned by 32, how about the size? Will a buffer has 23 elements be OK?

Thanks again!

[Pavel A.]

If no external devices involved, just try memcpy. No alignment should be needed.

-- pa

[PMath.4]

This is a really interesting question and one I'm struggling with. There seems to be particular issues when external SDRAM is involved and also instructions like LONGJMP. For example if I don't Clean and Invalidate Cache before a longjmp then in certain circumstances I get memory fault errors. I'm also seeing evidence of errors when memory manipulations span banks in SDRAM. All this is very difficult to track down as using the debugger changes behaviour completely rendering it useless. Some hard and fast guidance would be really useful.