What's the max voltage tolerance when STM32 is not powered?

[diverger]

I'm confused with the max voltage tolerance of STM32's GPIO.

1. In the datasheet, it states the max voltage of Vin is 4V for TT_xx pins. But in AN4899, it states they are Vdd + 0.3V. You see, the former has no relation with Vdd, it implies they will tolerant 4V even Vdd is 0V. But the later tells me, when Vdd is 0V, Vin can't go beyond 0.3V.
2. In the datasheet, it states the max voltage of Vin is 5.5V for FT_c pins and has no relation with Vdd. But in AN4899, it states when Vdd = 0V, the pins can only tolerant 3.6V.

Any help? Thanks.

[KDJEM.1]

Hi @diverger​,

In the datasheet, the voltage characteristics table provides the maximum voltage that the device can tolerate.

So, the user will operate their device with general operating conditions table descripted in the datasheet. Exposure to maximum rating conditions for extended periods may affect device reliability.

I think that the AN4899 is aligned with General operating conditions table description in the datasheet.

Note that the AN4899 does not give a description for FT_c (5 V tolerant I/O, USB Type-C PD capable) pins.

It is always advised to refer to the datasheet and precisely " General operating conditions table" to choose the adequate values.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Thanks

Kaouthar

[diverger]

Thanks for the reply.

So, what's the max voltage that TT_xx pins can tolerant, when Vdd = 0V?

Thanks.

[Peter BENSCH]

As @KDJEM.1​ said, you can find this information in the respective data sheet under Operating Conditions. As a rule, the voltage at VDD=0 must not exceed the value 0.3V, because otherwise internal parasitic pn junctions become conductive, which results in impermissible current flow:

I/O input voltage TT_xx I/O: min -0.3V, max VDDIOx+0.3

Does it answer your question?

Regards

/Peter

[diverger]

Yes, I see the TT_xx obey the general VDD+0.3V rule. In AN4899, for FT pins, it states (section 5.2.2):

When VDD = 0 V, the input voltage on the GPIO cannot exceed 3.6 V

So, FT pins are special here, they don't obey the VDD+0.3V rule, right?

Thanks.

[Peter BENSCH]

What you call the VDD+0.3V rule also only applies to the TT_xx I/O.

The same table in the respective data sheet states e.g.:

VIN (I/O input voltage) All I/O except BOOT0 and TT_xx: min 0.3V, max Min(Min(VDD, VDDA, [etc])+3.6 V, 5.5 V)

with footnotes like:

This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, [etc])+3.6 V and 5.5V.

This results in the statement in AN4899, as 0V+3.6V = 3.6V.

By the way, as Kaouthar has already pointed out, the data sheet is always primarily relevant. Further technical details can be found in the reference manuals, while the application notes typically only provide additional explanatory information or application examples.

Regards

/Peter