What's the lowest power way of using a Timer to divide by 2 ?

[MikeDB]

I need to divide a 24.576 MHz signal down to 12.288 MHz for a low power ADC so thought a timer would do this easily. But either I'm missing something or I have to put a value of 1 in the compare register and reload the counter all the time which seems rather wasteful on power. Is there a simpler way to just divide a signal by two by putting it in TIMx_ETR and outputting on one of the TIMx_CHy pins, presumably with the rest of the counter bits free-running ?

Thanks

[waclawek.jan]

Which STM32?

Is the 24.576 MHz signal an external signal unrelated to the STM32 system clock?

Probably the simplest is to get the 24.576 MHz serve as one of the two external clocks, set ARR=1 and one a spare channel one of the PWM modes and CCRx=1.

Note, that TIM are synchronous, so 1. given TIM internal clock has to be > 2x 24.576 MHz, 2. the output duty may be not 50:50.

JW

[MikeDB]

STM32F730.

The 24.576 comes from another device. No relation to the clocks in the F730. Just trying to save using a HC74 as I have spare pins on the F730.

Can live with not 50:50 but not with jitter.

[waclawek.jan]

LPTIM should be present except of the 64-pin package. LPTIM is asynchronous.

Unfortunately, ST traditionally gives NO (0) characterization data on LPTIM. I believe it should run at 24MHz clock OK.

JW

[MikeDB]

Yes I found LPTIM but unfortunately I'm using the 64 pin package. Spec I found was 16MHz. I'll go back to using a HCMOS divider :(

Many thanks for trying.

[waclawek.jan]

> Spec I found was 16MHz.

Where?

JW

[MikeDB]

AN4865, end section 5. 15MHz, not 16MHz, but not clear if that is all the time or just when the rest of the IC is stopped.

[waclawek.jan]

Thanks.

JW